引言
本文在上一讲逐渐熟悉了VCS的开关选项后,下面继续介绍VCS的使用,我始终关注于熟悉工具的使用,在本系列中,对Verilog的语法不作深入研究,这样可以加快前进的步伐。也为了加快从FPGA中转变到IC领域来。在本文中将介绍VCS 调试基础。
1、基础理论讲义
—Afer completing this unit ,you should be able to:
- Describe three methods of debugging Verilog code using VCS
- Invoke UCLI debugger
- Debug Verilog designs using UCLI
–VCS Debugging Suport
4. Trance and locate causes of errors
5. Three general debugging methods:
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Verilog SystemVerilog System Task calls
VCS UCLI
VCS DVE(GUI) -
Four factors to consider:
simulation speed
signal visibility
sgnal tractability
usability
Verilog System Task For Debugging 利用verilog的系统函数
- Debug visibility:
- $ display prints formatted message to console
- $ strobe Like$dispaly except printing is delayed until all events in the current time step have executed
- $ monitor Monitor signals listed and prints formatted message whenever one of the listed signals changes
- $ time returns current simulation time as a 64bits integer
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Stopping simulations:
$stop halts simulation lie a breakpoint
$finish halts simulation and terminated the simulation session -
Simulation stimulus and reference:
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−
readmemh Reads ASCII data from a disk file,each digit is hexadecimal -
readmemhReadsASCIIdatafromadiskfile,eachdigitishexadecimal− readmemb
Reads ASCII dataform a disk file ,Each digit is binary
Debugging via UCLI(no-recom)不推荐使用UCLI方式来查看波形
- Simulation speed
Speed depends on the scale of visibility you specify - Signal Vsisibiility
- Signal Traceability
-Usability
Compile and Invoke UCLI Debugger
-Compile and invoke UCLI in one step(一步走,编译并且调用UCLI)
$ vcs source.v -debug|debug_all -R -ucli
-ucli invokes UCLI and stop simulation time at time 0
-Compile and invoke UCLI in two step(分两步走,先编译,后执行可执行文件)
vcs source.v -debug|debug_all|debug_pp(debug_pp只打开部分调试开关,加快编译速度)
invoke UCLI and stop simulation time at time 0
$simv -ucli
UCLI Debugger Command Line Option
-debug
enables command line debugging option. This flag does not enable line stepping.
-debug_all
enables command line debugging option including line stepping
-ucli
forces runtime to go into UCI mode by default
-gui
compile time option invokes the DVE gui when issured at run time
-l log_filename
captures simulation output ,such as user input UCLI commands and responses to UCLI commands.
-i input_filename
reads interactive UCLI commands from a file the switches readding from standard command line input
-k key_filename
writes interactive commands entered to input_filename,which can be used by a latter simv as -i input_filename
由于UCLI的陈旧,这里不再强调。
退出UCLI
quit 即可
Problems in simulation?
if you suspect simlation is having problems
Determine whether or not time is advancing:
halt simulation by hiting ctrl+c 通过ctrl+c来退出仿真
check simulation time
continue simulation by typing in run at UCLI prompt
halt simulation again after a shor period of time
if simulation time has not changed,simulation may be caught in infinite loop or waiting for a phantom triger
-Determine potential location of problem:
Re-compile with -debug_all compile-time option
halt simulation
use UCLI command show to dispaly variables
trace code execution with UCLI command next
官方的文档位置:
DVE(Discovery Visual Environment)
An intuitive and easy to use GUI
Quiickly fine bugs
RTL or Gates
Assertions
Testbench
Supports
Interactive
Post-simulaton analisis
Multiple languages
verilog
VHDL
SV
C++、C
NTB
波性文件vpd
verdi里面的波性文件为fsdb
比较两个信号
2、实际基本操作dve的技巧-图形界面参考资料
2.1 查看波形与调试波形
参考资料 DVE使用手册
以后在实验中逐步训练加强。
程序,我们仍然使用在卷一中讲解的程序。并且用DVE打开。界面如下:
主要分为:菜单、左边的模块、coding、下面的脚本、以及终端输出反馈。
DVE界面也有很多操作,涉及到了很多原理,我们不用一一来学,先上手搞懂基本操作再说,基本操作就是会看波形,把仿真跑起来。
首先是添加波形,我这里不好截图,选中波形后,右键即可,
add to waves->new wave
如图已经打开了波形,现在先运行起来再说。
有个向下箭头,这个就是运行。或者点击快捷键F5,然后波形就出来了,此时肯定不太好看,希望看到一个full。使用按下F即可,或界面按钮。
旁边是放大缩小。
此时我明白你肯定希望像在modelsim中一样,按住ctrl键滚动齿轮,对局部进行拉大。
在DVE中,使用鼠标左键不放拖动,就可以在指定的区域进行放大了。而且非常有趣的是,分为横向拖动和纵向拖动,纵向拖动是看full,还有斜着拖动,斜着拖动是看缩小,横向拖动是放大。
另外,在DVE中按住ctrl键,滚动齿轮,是波形向前向后。
然后可以右键可以add marker
2.2 基本入门
使用dve -v
或者在DVE的命令行输入gui_get_version
或者在help->about帮助菜单选项
可以查看到DVE的版本,DVE和VCS的版本要一致才行
在simulator中的选择setup,然后执行文件选择simv文件即可
该按钮可以用来重启波形