read_verilog -netlist sys.vg
current_design
link
#-------scan configuration-------------
set_scan_configuration -add_lockup true
set_scan_configuration -chain_count 12
set_scan_configuration -clock_mixing mix_clocks
set_scan_configuration -create_dedicated_Scan_out_ports false
echo "size is [sizeof_col [get_cells -hierar -filter "is_hierarchical == false && ref_name =~TLATNTSCAX* && full_name =~