STM32寄存器版本(基于架构ARM v7 F103ZET6)
最近用了很久的库函数版本STM32编程,后来发现其中很多原理及过程不是很理解,最终决定以寄存器版本为切入点,重新把cotex-m3系列的芯片之一进行再次深入的了解。我会根据自己的实践经验分享一些实验过程中的经验,现记录如下:
代码如下
目录如下:
实验6:独立看门狗
实验7:窗口看门狗
实验8 定时器中断
实验9:PWM实验
实验6:独立看门狗
#include "IWDG.h"
void idwg_init(u32 prer,u32 rlr)//prescaler,rlr,reload data{
IWDG->KR=0x5555;//enable pr and rlr register
IWDG->PR=prer;
IWDG->RLR=rlr;
IWDG->KR=0xAAAA;
IWDG->KR=0xCCCC;//start IWDG
}
void idwg_feed(void)//feed dog
{
IWDG->KR=0xAAAA;//reload
}
实验7:窗口看门狗
(通俗解释就是只能在规定的窗口内喂狗,不然就产生复位,主要解决独立看门狗的缺点如程序跑飞又跑回,这个时候独立看门狗一般不会产生复位)
#include "WWDG.h"
#include "led.h"
u8 WWDG_CNT=0x7f;//WWDG_CR register max num
void wwdg_init(u16 w,u8 wdgtb,u8 t)//w->W[6:0],wdgtb->WDGTB,t->T[5:0]
{
//1,enable clock
RCC->APB1ENR|=1<<11;//enable clock
//2,configuation CFR and CR register
WWDG_CNT=t&WWDG_CNT;
WWDG->CFR|=wdgtb<<7;
WWDG->CFR&=0xFF80;
WWDG->CFR|=w;
WWDG->CR|=WWDG_CNT;
WWDG->CR|=1<<7;//ENABLE WWDG
MY_NVIC_Init(0,0,WWDG_IRQn,2);
WWDG->SR=0x00;//clear early wakeup interrupt flag
WWDG->CFR|=1<<9;
}
void WWDG_set_counter(u8 cnt)//reset counter
{
WWDG->CR|=(cnt&0x7f);
}
void WWDG_IRQHandler(void)
{
WWDG_set_counter(WWDG_CNT);
WWDG->SR=0x00;//clear early wakeup interrupt flag
LED1=!LED1;
}
实验8 定时器中断
#include "timer_inter.h"
#include "led.h"
void timeinter_init(u32 ARR,u32 psc)
{
//ENABLE clock
RCC->APB1ENR|=1<<1;
//configuation TIM3
//tout=(arr+1)*(psc+1)/Tclock;
//system clock 72MHz,Tclock=72MHzÈôÏ붨ʱ¼ä¸ôΪ1s£¬ÒÔ10KHzΪ¼ÆÊýƵÂÊ£ºpsc=7199
//ARR=9999
TIM3->ARR|=ARR;
TIM3->PSC|=psc;
TIM3->DIER|=1<<0;//update interrupt enable
TIM3->CR1|=1<<0;//start TIM3
MY_NVIC_Init(0,0,TIM3_IRQn,2);
}
void TIM3_IRQHandler(void)
{
if(TIM3->SR&(0x0001))//update interrupt flag
{
LED1=!LED1;
}
TIM3->SR&=~(1<<0);//clear update interrupt flag
}
实验9:PWM实验
//function:pwm control PB5(led0)
#include "PWM.h"
void pwm_init(u16 arr,u8 psc)
{
//ENABLE TIM3 clock and configuating PB5 for AFIO
RCC->APB1ENR|=1<<1;
RCC->APB2ENR|=1<<3;//
GPIOB->CRL&=0xFF0FFFFF;
GPIOB->CRL|=0x00B00000;//GPIO_Mode_AF_OD.50MHz
//confguating AFIO_MAPR regisetr,if you want to cnfiguate AFIO register
// you must Alternate function I/O clock enable
RCC->APB2ENR|=1<<0;
AFIO->MAPR&=0xFFFFF3FF;//clear tim3[11,10]
AFIO->MAPR|=0x00000800;//remap to PB5
//configuating ARR and PSC
TIM3->ARR=arr;
TIM3->PSC=psc;
//CCMR1
TIM3->CCMR1|=7<<12;//TIMx_CNT<TIMx_CCR1 chanel 1 invalid,PWM2
TIM3->CCMR1|=1<<11;//Output compare 2 preload enable
//ENABLE CH2 and ENABLE TIM3(CCER1 and CR)
TIM3->CCER|=1<<4;
TIM3->CR1|=1<<7;//Auto-reload preload enable
TIM3->CR1|=1<<0;
}