名称:四位十进制频率计VHDL,DE1开发板验证
软件:Quartus
语言:VHDL
要求:
数字频率计设计要求
1、四位十进制数字显示的数学式频率计,其频率测量范围为10~9999khz,测量单位为kHz。
2、要求量程能够转换。即测几十到几百千(kHz)时,有小数点显示,前者显示小数点后2位,后者显示小数点后1位。
3、当输入的信号小于10kHz时,输出显示全0;当输入的信号大于9999kHz
时,输出显示全H。
FPGA代码资源网:hdlcode.com
本代码已在DE1开发板验证,开发板照片如下:
部分代码展示
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; --计数器模块 ENTITY counter IS PORT ( signal_in : IN STD_LOGIC;--被测信号 en : IN STD_LOGIC;--1mS闸门信号 rst : IN STD_LOGIC;--复位 alarm : OUT STD_LOGIC;--报警 number : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)--频率值 ); END counter; ARCHITECTURE trans OF counter IS SIGNAL num_0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; BEGIN number <= (num_3 & num_2 & num_1 & num_0);--单位Hz --计数,计数1s内的信号周期数,计数值就是频率值 PROCESS (signal_in, rst) BEGIN IF (rst = '1') THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= "0000"; num_3 <= "0000"; alarm <= '0'; ELSIF (signal_in'EVENT AND signal_in = '1') THEN IF (en = '1') THEN--计数,低位都是9,则高位加1,低位清零,例如加到999,则变为1000 IF (num_3 = "1001" AND num_2 = "1001" AND num_1 = "1001" AND num_0 = "1001") THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= "0000"; num_3 <= "0000"; alarm <= '1';--报警 ELSIF (num_2 = "1001" AND num_1 = "1001" AND num_0 = "1001") THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= "0000"; num_3 <= num_3 + "0001";--低位为9,则高位加1,低位清零 alarm <= '0'; ELSIF (num_1 = "1001" AND num_0 = "1001") THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= num_2 + "0001";--低位为9,则高位加1,低位清零 num_3 <= num_3; alarm <= '0'; ELSIF (num_0 = "1001") THEN num_0 <= "0000"; num_1 <= num_1 + "0001";--低位为9,则高位加1,低位清零 num_2 <= num_2; num_3 <= num_3; alarm <= '0'; ELSE num_0 <= num_0 + "0001";--低位加1 num_1 <= num_1; num_2 <= num_2; num_3 <= num_3; alarm <= '0'; END IF; END IF; END IF; END PROCESS; END trans;
设计文档(文档点击可下载):
1. 工程文件
2. 程序文件
3. 程序编译
4. 管脚分配
5. 仿真图
整体仿真图
计数器模块
锁存器模块
控制模块
产生闸门信号,清零信号,锁存信号
数码管显示模块