module mux2_1
{
input wire in_1,
input wire in_2,
input wire sel,
output reg out
);
always@(*)
if (sel==1'b1)
out=in_2;
else
out=in_1;
endmodule
verilog mux2_1
最新推荐文章于 2024-04-27 00:15:00 发布
module mux2_1
{
input wire in_1,
input wire in_2,
input wire sel,
output reg out
);
always@(*)
if (sel==1'b1)
out=in_2;
else
out=in_1;
endmodule