【verilog学习25】HDLBits：Verification: Writing testbenches

I Tb/clock

1.代码编写

`timescale 1ps/1ps
module top_module ( );
    reg clk; 
    
    initial
        clk = 1'b0;

    always #5 clk = ~clk;
    
    dut instance1(
        .clk(clk));
endmodule

2.提交结果

Success

3.题目分析

You are provided a module with the following declaration:

module dut ( input clk ) ;

Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the module’s clk input. The clock has a period of 10 ps. The clock should be initialized to zero with its first transition being 0 to 1.

分为：声明、初始化、赋值、例化四个模块。
timescale 时间延迟与时间精度。

`timescale 1ns/100ps
表示时间延迟单位 1ns，时延精度100ps，5.2表示5.2ns。

`timescale 10ns/1ns
表示时间延迟单位10ns，时延精度1ns，5.2表示52ns。
clk是test文件的输入，所以是testbench文件的输出，所以clk在testbench中定义为reg型。

II Testbench1 (Tb/tb1)

1.代码编写

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
        A = 1'b0;
        B = 1'b0;
        #10 A = 1'b1;
        #5 B = 1'b1;
        #5 A = 1'b0;
        #20 B = 1'b0;
    end
    

endmodule

// 复习fork_join
module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial fork
        A = 1'b0;
        B = 1'b0;
        #10 A = 1'b1;
        #15 B = 1'b1;
        #20 A = 1'b0;
        #40 B = 1'b0;
    join
    

endmodule

2.提交结果

Success

3.题目分析

initial begin_end是串行，其中的时间延迟累加。
initial fork_join是并行，其中的时间延迟直接对应相应时刻。

III AND gate (Tb/and)

1.代码编写

module top_module();
    reg [1:0] in;
    wire out;
    initial begin
        in = 2'b00;
        #10 
        in[0] = 1'b1;
        #10 
        in[0] = 1'b0;
        in[1] = 1'b1;
        #10
        in[0] = 1'b1;
        
    end
    andgate instance1(
        .in(in),
        .out(out)
    );
endmodule

2.提交结果

Success

3.题目分析

You are given the following AND gate you wish to test:

module andgate (
    input [1:0] in,
    output out
);

Write a testbench that instantiates this AND gate and tests all 4 input combinations, by generating the following timing diagram:

out是test输出，所以是testbench输入，所以在testbench里为wire（net）型变量。
out在test文件里计算，之后通过testbench例化来显示其波形。

IV Testbench2 (Tb/tb2)

1.代码编写

module top_module();
    reg clk,in;
    reg [2:0] s;
    wire out;
    initial begin
        clk = 1'b0;
        in = 1'b0;
        s = 3'd2;
        #10
        s = 3'd6;
        #10 //20
        s = 3'd2;
        in = 1'b1;
        #10 //30
        s = 3'd7;
        in = 1'b0;
        #10 //40
        s = 3'd0;
        in = 1'b1;
        #30 //70
        in = 1'b0;
        
    end
    always #5 clk = ~clk;
    q7 instance1(
        .clk(clk),
        .in(in),
        .s(s),
        .out(out)
    );
endmodule

2.提交结果

Success

3.题目分析

The waveform below sets clk, in, and s:

Module q7 has the following declaration:

module q7 (
    input clk,
    input in,
    input [2:0] s,
    output out
);

Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.

V T flip-flop Tb/tff

1.代码编写

module top_module ();
	reg clk,reset,t;
    wire q;
    initial begin
        clk = 1'b1;
        reset = 1'b0;
        t = 1'b0;
        #10
        reset = 1'b1;
        #2
        reset = 1'b0;
        t = 1'b1;
        #2
        t = 1'b0;
    end
    always #1 clk = ~clk;
    tff instance1(
        .clk(clk),
        .reset(reset),
        .t(t),
        .q(q)
    );
endmodule

2.提交结果

Success

3.题目分析

You are given a T flip-flop module with the following declaration:

module tff (
    input clk,
    input reset,   // active-high synchronous reset
    input t,       // toggle
    output q
);

Write a testbench that instantiates one tff and will reset the T flip-flop then toggle it to the “1” state.
这题是比较自由的。
只要满足toggle比reset晚1cycle即可。
注意，时钟上升沿触发，

always #1 clk = ~clk;

这样的时钟周期是2而非1。