[UVM]UVM TLM FIFO使用方法總結

                     UVM TLM FIFO用法總結

 

  • 目录

一、TLM FIFO Overview

二、TLM FIFO Classes

三、TLM FIFO Methods

3.1、new

3.2、size

3.3、used

3.4、is_empty

3.5、is_full

3.6、flush

四、Summary of TLM FIFOs


       The TLM FIFO provides storage for the transactions between two independently running processes. We have seen put and get methods operates with only one outstanding transaction at a time i.e it is allowed to send the transaction Only after consumption of the previously sent transaction, in this case, the sender and receiver must be in sync else lead to blocking in one of the components.

       What if the case where the sender needs not wait for the receiver acknowledgment, it just wants to store it in memory and the receiver can consume whenever required. in this sender and The receiver needs not to be in sync. Yes With TLM FIFO it is possible.

            

 

一、TLM FIFO Overview

  • In TLM FIFO, the sender pushes the transactions to FIFO and whenever it required reiver pops it out or fetches from the FIFO
  • Transactions are put into the FIFO via the put_export method
  • Transactions are fetched from the FIFO via the get_peek_export method
  • As its FIFO (First In First Out), transactions are fetched from the FIFO in the order they are put

 

二、TLM FIFO Classes

uvm_tlm_fifo #(T)

       This class provides storage of transactions between two independently running processes

 

三、TLM FIFO Methods

3.1、new

  •   This is a constructor method used for the creation of TLM FIFO
function new (string name,
              uvm_component parent,
              int size=1);
  • The name and parent are the normal uvm_component constructor arguments
  • The size indicates the maximum size of the FIFO; a value of zero indicates no upper bound

3.2、size

  • Calling size() returns the size of the FIFO
  • A return value of 0 indicates the FIFO capacity has no limit

3.3、used

  • Returns the number of entries put into the FIFO

3.4、is_empty

  • Returns 1 when there are no entries in the FIFO, 0 otherwise

3.5、is_full

  • Returns 1 when the number of entries in the FIFO is equal to its size, 0 otherwise

3.6、flush

  • Calling flush method will Remove all entries from the FIFO
  • after the flush method call used method returns 0 and the is_empty method returns 1

 

四、Summary of TLM FIFOs

             

 

五、TLM Analysis FIFO Example

 5.1、

            

 5.2 

           

 

 5.2、Implementing analysis port in comp_a

class component_a extends uvm_component;
  
  transaction                             trans;
  //Step-1. Declaring analysis port
  uvm_analysis_port#(transaction)         analysis_port;
  
  `uvm_component_utils(component_a)
  
  //---------------------------------------
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    
    //Step-2. Creating analysis port
    analysis_port = new("analysis_port", this);
  endfunction : new
  //---------------------------------------
  // run_phase
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    
    trans = transaction::type_id::create("trans", this);
    void'(trans.randomize());
    `uvm_info(get_type_name(), $sformatf(" tranaction randomized"), UVM_LOW)
    `uvm_info(get_type_name(), $sformatf(" Printing trans, \n %s", trans.sprint()), UVM_LOW)
    
    `uvm_info(get_type_name(),$sformatf(" Before calling port write method"),UVM_LOW)
    //Ste-3. Calling write method
    analysis_port.write(trans);
    `uvm_info(get_type_name(), $sformatf(" After  calling port write method"), UVM_LOW)
    
    phase.drop_objection(this);

  endtask : run_phase

endclass : component_a

 5.3、Implementing analysis FIFO in comp_b

class component_b extends uvm_component;
  
  transaction                              trans;
  //Step-1. Declaring analysis FIFO
  uvm_tlm_analysis_fifo #(transaction)     analy_fifo;  
  `uvm_component_utils(component_b)
  
  //---------------------------------------
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    //Step-2. Creating analysis FIFO
    analy_fifo = new("analy_fifo", this);
  endfunction : new
  
  //---------------------------------------
  // run_phase
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    
    #100;
    `uvm_info(get_type_name(), $sformatf(" Before calling analysis fifo get method"), UVM_LOW)
    //Step.3 - Getting trans from FIFO
    analy_fifo.get(trans);
    `uvm_info(get_type_name(), $sformatf(" After  calling analysis fifo get method"), UVM_LOW)
    `uvm_info(get_type_name(), $sformatf(" Printing trans, \n %s",trans.sprint()), UVM_LOW)
    
    phase.drop_objection(this);

  endtask : run_phase

endclass : component_b

5.4、Connecting analysis port and analysis FIFO in env

function void connect_phase(uvm_phase phase);
  //Connecting analysis port to analysis FIFO
  comp_a.analysis_port.connect(comp_b.analy_fifo.analysis_export);
endfunction : connect_phase

 

<think>好的,我需要回答用户关于UVM TLM FIFO常见用法、示例和代码的问题。首先,我得回顾一下用户提供的引用内容,确保信息准确。引用[1]提到uvm_tlm_analysis_fifo有各种方法管理事务,比如写入、读取、清空等。引用[3]详细说明了uvm_tlm_fifo作为参数化FIFO,连接生产者和消费者的常见方法,以及构造函数中的最大深度参数。 用户需要常见用法和示例代码,我应该先解释uvm_tlm_fifo的基本概念,比如它如何作为中间组件连接不同端口,比如put和get接口。然后给出一个典型的使用场景,比如连接producer和consumer组件。接着,我需要提供一个代码示例,展示如何声明FIFO,如何在build_phase中创建实例,以及如何连接各个端口。 需要注意的是,FIFO的深度默认是1,但可以根据需求调整。此外,uvm_tlm_analysis_fifo是专门用于analysis端口的变体,可能也需要提及。在代码示例中,应该包括producer、consumer和FIFO的连接方式,比如使用put_port连接到fifo.put_export,以及consumer的get_port连接到fifo.get_export。 另外,用户可能对FIFO方法感兴趣,比如put和get操作,可以简要说明这些方法使用,但代码示例中可能不需要详细展示,因为重点在于连接方式。最后,应该生成相关问题,帮助用户进一步学习,比如FIFO深度的影响、与普通FIFO的区别,以及处理阻塞的方法。 需要确保所有技术术语正确,代码符合UVM标准,并且引用正确的来源。同时,按照用户的格式要求,使用中文回答,行内公式正确,独立公式单独成段,但这里可能不需要数学公式。最后,检查引用标识是否正确添加到对应的位置,比如引用[1]、[3]的相关内容。</think>### UVM TLM FIFO 常见用法与示例 UVM TLM FIFOUVM 验证环境中实现组件间事务通信的核心组件,主要用于解耦生产者和消费者,同时提供缓冲功能。以下是其常见用法及示例: --- #### **1. 基本连接与实例化** **作用**:作为中间组件连接 `put` 端口和 `get` 端口,实现事务传递。 **代码示例**: ```systemverilog class producer extends uvm_component; uvm_blocking_put_port #(transaction) put_port; // ... 其他代码 endclass class consumer extends uvm_component; uvm_blocking_get_port #(transaction) get_port; // ... 其他代码 endclass class env extends uvm_env; producer prod; consumer cons; uvm_tlm_fifo #(transaction) fifo; virtual function void build_phase(uvm_phase phase); fifo = new("fifo", this); // 默认深度为1 prod = producer::type_id::create("prod", this); cons = consumer::type_id::create("cons", this); endfunction virtual function void connect_phase(uvm_phase phase); prod.put_port.connect(fifo.put_export); // 生产者写入FIFO cons.get_port.connect(fifo.get_export); // 消费者从FIFO读取 endfunction endclass ``` **关键点**: - 通过 `put_export` 和 `get_export` 连接端口,实现事务的异步传输[^3]。 - FIFO 深度可配置(例如 `new("fifo", this, 5)` 设置深度为5)。 --- #### **2. 非阻塞通信** **作用**:通过 `try_put` 和 `try_get` 避免阻塞行为。 **代码片段**: ```systemverilog // 生产者尝试写入事务 if (fifo.try_put(trans)) $display("写入成功"); else $display("FIFO已满"); // 消费者尝试读取事务 if (fifo.try_get(trans)) $display("读取成功"); else $display("FIFO为空"); ``` --- #### **3. 与 Analysis FIFO 结合** **作用**:`uvm_tlm_analysis_fifo` 支持广播事务到多个消费者。 **示例**: ```systemverilog uvm_analysis_port #(transaction) analysis_port; uvm_tlm_analysis_fifo #(transaction) analysis_fifo; // 连接分析端口和FIFO analysis_port.connect(analysis_fifo.analysis_export); // 多个消费者可订阅同一FIFO consumer1.get_port.connect(analysis_fifo.get_export); consumer2.get_port.connect(analysis_fifo.get_export); ``` **特点**
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