基于FPGA-用verilog语言描绘3种led灯状态变化，采用嵌套方式实现

用verilog的状态机设计3种led灯状态变化，采用嵌套方式实现。
（1） 8路彩灯同时亮灭；
（2） 从左至右逐个亮（每次只有1路亮）；
（3） 8路彩灯每次4路灯亮，4路灯灭，且亮灭相间，交替亮灭。

module   color_led(

input     wire       clk,
input     wire       rst,
output    reg [7:0]  led


);

//定义计时器
reg [25:0] cnt=0;
localparam T=50_000_000;

always@(posedge clk or posedge rst) begin

if(rst)
	cnt<=0;
else if(cnt==T-1)
	cnt<=0;
else
    cnt<=cnt+1;
end 


reg  [1:0] out;        //定义3个外层状态

localparam   out0=0;
localparam   out1=1; 
localparam   out2=2;

reg [1:0] out0_in;     //8路同时亮灭
localparam   out0_in0=0;
localparam   out0_in1=1; 

reg [2:0] out1_in;     //每次亮1路
localparam   out1_in0=0;
localparam   out1_in1=1; 
localparam   out1_in2=2;
localparam   out1_in3=3; 
localparam   out1_in4=4;
localparam   out1_in5=5; 
localparam   out1_in6=6;
localparam   out1_in7=7; 

reg [1:0] out2_in;     //亮灭相间
localparam   out2_in0=0;
localparam   out2_in1=1; 

reg [4:0] count=0;   //计数

always@(posedge clk or posedge rst) begin


if(rst) begin
	out<=0;
	out0_in<=0;
	out1_in<=0;
	out2_in<=0;
end
	
else  
	
	case(out)
			out0    :     begin
								if(cnt==T-1 && count==5) begin
									out<=out1;
									count<=0;
								end	
								else if(cnt==T-1) 
								   
									count<=count+1;
								
								case(out0_in)
									 out0_in0   :      begin
															    led<=8'b1111_1111;
																if(cnt==T-1)
																	out0_in<=out0_in1;
																else
																    out0_in<=out0_in0;
										               end
									 out0_in1   :      begin
															    led<=8'b0000_0000;
																if(cnt==T-1)
																	out0_in<=out0_in0;
																else
																    out0_in<=out0_in1;
										               end
									default      : ;
									endcase
			
			                end
							
							
			out1    :     begin
								if(cnt==T-1 && count==8) begin
									out<=out2;
									count<=0;
								end	
								else if(cnt==T-1) 
								   
									count<=count+1;
								
								case(out1_in)
									 out1_in0   :      begin
															    led<=8'b1000_0000;
																if(cnt==T-1)
																	out1_in<=out1_in1;
																else
																    out1_in<=out1_in0;
										               end
									 out1_in1   :      begin
															    led<=8'b0100_0000;
																if(cnt==T-1)
																	out1_in<=out1_in2;
																else
																    out1_in<=out1_in1;
										                end
			                         out1_in2   :      begin
															    led<=8'b0010_0000;
																if(cnt==T-1)
																	out1_in<=out1_in3;
																else
																    out1_in<=out1_in2;
										               end
									 out1_in3   :      begin
															    led<=8'b0001_0000;
																if(cnt==T-1)
																	out1_in<=out1_in4;
																else
																    out1_in<=out1_in3;
										                end
			                         out1_in4   :      begin
															    led<=8'b0000_1000;
																if(cnt==T-1)
																	out1_in<=out1_in5;
																else
																    out1_in<=out1_in4;
										               end
									 out1_in5   :      begin
															    led<=8'b0000_0100;
																if(cnt==T-1)
																	out1_in<=out1_in6;
																else
																    out1_in<=out1_in5;
										                end
			                         out1_in6   :      begin
															    led<=8'b0000_0010;
																if(cnt==T-1)
																	out1_in<=out1_in7;
																else
																    out1_in<=out1_in6;
										               end
									 out1_in7   :      begin
															    led<=8'b0000_0001;
																if(cnt==T-1)
																	out1_in<=out1_in0;
																else
																    out1_in<=out1_in7;
										                end
									 default     : ;
						             endcase			 
			                end


			out2    :     begin
								if(cnt==T-1 && count==5) begin
									out<=out0;
									count<=0;
								end	
								else  if (cnt==T-1)
								    
									count<=count+1;
								
								case(out2_in)
									 out2_in0   :      begin
															    led<=8'b1010_1010;
																if(cnt==T-1)
																	out2_in<=out2_in1;
																else
																    out2_in<=out2_in0;
										               end
									 out2_in1   :      begin
															    led<=8'b0101_0101;
																if(cnt==T-1)
																	out2_in<=out2_in0;
																else
																    out2_in<=out2_in1;
										               end
									default      : ;
									endcase
			
			                end
            default: ;
			endcase
							
end


endmodule