FPGA 移位寄存器检测串行序列(Verilog)

MAIN CODE

/*----------------------------------------------
从输入数据串检测'Y'(0x59)字符,成功检测后，
给出一个时钟周期的flag信号y。使用时需注意移位寄存器的时钟频率。
d：输入数据串
y：flag
----------------------------------------------*/

module work(clk, reset, d, y);
	//输入输出端口定义
	input clk, reset, d;
	output reg y;
    
    reg [7:0]sda_reg;
    reg [7:0]judge_reg;

	reg data1;
	reg data2;

//输入信号同步
always@(posedge clk or negedge reset)
begin
    if(!reset)
        begin
            data1 <= 1'b0;
            data2 <= 1'b0;
        end
    else
        begin
        data1 <= d;
        data2 <= data1;
        end
end

//串入并出，8bit移位寄存器，最高位(7)自动抹去，最低位(0)补为当前输入数据。    
always@(posedge clk or negedge reset)
    begin
        if(!reset)
            begin
                sda_reg<=0;
            end
        else
            begin
                if(1)//可用作使能
                    begin
                        sda_reg<={sda_reg[6:0],data2};  
                    end
                else
                    begin
                        sda_reg<=0;
                    end
            end
    end

//将串入并出，8bit移位寄存器，每个时钟周期的输出结果加以判断，如果是待检测序列，就将其抹掉！
always@(posedge clk or negedge reset)
    begin
        if(!reset)
            begin
                judge_reg <= 8'd0;
                y <= 1'd0;
            end
        else if(sda_reg == 8'h59)
            begin
                judge_reg <= 8'hzz;
                y <= 1'd1;
            end
        else
            begin
                judge_reg <= sda_reg;
                y <= 1'd0;
            end
    end
endmodule

SEND CODE

/*----------------------------------------------
序列发生器：发送固定序列：16'h559A
----------------------------------------------*/
module send(clk, reset, y);
    input clk, reset;
	output reg y;
   
    reg[15:0] data = 16'h559A;
    reg[4:0] cnt;
    
	always@(posedge clk or negedge reset)
	begin
		if(!reset)
            cnt <= 5'd0;
		else if(cnt < 5'd16)
            cnt <= cnt + 1'b1;
        else
            cnt <= 5'd0;
    end 

	always@(posedge clk or negedge reset)
	begin
		if(!reset)
            y <= 1'b0;
		else
			begin
                case(cnt)
                5'd1: y <= data[15];
                5'd2: y <= data[14]; 
                5'd3: y <= data[13]; 
                5'd4: y <= data[12]; 
                5'd5: y <= data[11]; 
                5'd6: y <= data[10]; 
                5'd7: y <= data[9]; 
                5'd8: y <= data[8]; 
                5'd9: y <= data[7]; 
                5'd10: y <= data[6]; 
                5'd11: y <= data[5]; 
                5'd12: y <= data[4];
                5'd13: y <= data[3]; 
                5'd14: y <= data[2]; 
                5'd15: y <= data[1]; 
                5'd16: y <= data[0]; 
                default:y <= 1'b0;
                endcase
			end
	end    
endmodule

TOP CODE

module top(clk1,rst1,y);

input clk1;
input rst1;

wire wire_link;
output y;


send send1(
            .clk(clk1), 
            .reset(rst1), 
            .y(wire_link)
            );
work work1(
             .clk(clk1),
             .reset(rst1),
             .d(wire_link),
             .y(y)
             );
endmodule

TEST BENCH

`timescale 1ns/1ns
module testbench;

reg clk1;
reg rst1;

wire y;

    top top1(
            .clk1(clk1),
            .rst1(rst1),
            .y(y)
            );

    initial clk1 = 1'b1;
    always#10 clk1 = ~clk1;
    
    initial begin
        rst1 = 1'b0;    //未运行状态

        #400;
        rst1 = 1'b1;


        #600;
        //@(posedge send_done1) //等待发送完成信号的上升沿
        $stop;
    end
endmodule