PCIE知识点-020：谈谈bus master en

Bus master en信号

Type0的function：控制function发起Memory and I/O Read/Write Requests

1. Bus Master Enable为0，不允许function发起Memory and I/O Read/Write Requests
2. PF的Bus Master Enable 位于PF配置空间的Command Register的bit2，仅仅控制PF自身的请求，不会控制所属VF的请求
3. VF的Bus Master Enable，位于VF配置空间的Command Register的bit2，仅仅控制VF自身的请求

Type1的function：控制function向Upstream方向转发Memory and I/O Read/Write Requests

1. Switch upstream port的Bus Master Enable为0，
   1. 会将downstream side收到的Memory and I/O Read/Write Requests当做UR处理
   2. Switch upstream port自身不允许向upstream 方向发出Memory and I/O Read/Write Requests

参考文档：PCI Express Base Specification, Rev. 5.0 Version 1.0

Bus Master Enable - Controls the ability of a Function to issue Memory and I/O Read/Write Requests, and the ability of a Port to forward Memory and I/O Read/Write Requests in the Upstream direction • Functions with a Type 0 Configuration Space Header: When this bit is Set, the Function is allowed to issue Memory or I/O Requests. When this bit is Clear, the Function is not allowed to issue any Memory or I/O Requests. Note that as MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master Enable bit to 0b disables MSI/MSI-X interrupt Messages as well. Requests other than Memory or I/O Requests are not controlled by this bit. Default value of this bit is 0b. This bit is hardwired to 0b if a Function does not generate Memory or I/O Requests. • Functions with a Type 1 Configurations Space Header: This bit controls forwarding of Memory or I/O Requests by a Port in the Upstream direction. When this bit is 0b, Memory and I/O Requests received at a Root Port or the Downstream side of a Switch Port must be handled as Unsupported Requests (UR), and for Non-Posted Requests a Completion with UR Completion Status must be returned. This bit does not affect forwarding of Completions in either the Upstream or Downstream direction. The forwarding of Requests other than Memory or I/O Requests is not controlled by this bit. Default value of this bit is 0b.