基于FPGA的数字洗衣机Verilog开发Modelsim仿真

链接：https://pan.baidu.com/s/1dUKtiykRin3chAq48nOMkg
提取码：ipmz

部分参考代码

(末尾附文件)

module XiYiJi(
	input clk,
	input reset_n,
	
	input add_set,
	input start_set,
	
	input stop_set,
	
	output led_1,
	output led_2,
	output led_3,
	
	output [5:0] sm_cs,
	output [7:0] sm_db,
	output alarm
);

wire add_set_r;
wire start_set_r;
wire stop_set_r;

reg [3:0] looptimes;
reg [3:0] actualtimes;

reg [11:0] clk_100us_cnt;
reg clk_100us_tmp;
reg [3:0] scan_cnt;
reg [3:0] data;

wire clk_1s;

reg led_1_r;
reg led_2_r;
reg led_3_r;

reg [5:0] sm_cs_r;
reg [7:0] sm_db_r;

reg alarm_r;
reg alarm_o;

reg status_1;
reg status_2;
reg status_3;
reg status_4;
reg status_5;

reg [7:0] cnt;

reg [7:0] cnt1;
reg [7:0] cnt2;
reg [7:0] cnt3;
reg [7:0] cnt4;
reg [7:0] cnt5;

wire [1:0] cnt1_bai;
wire [3:0] cnt1_shi;
wire [3:0] cnt1_ge;

wire [1:0] cnt2_bai;
wire [3:0] cnt2_shi;
wire [3:0] cnt2_ge;

wire [1:0] cnt3_bai;
wire [3:0] cnt3_shi;
wire [3:0] cnt3_ge;

wire [1:0] cnt4_bai;
wire [3:0] cnt4_shi;
wire [3:0] cnt4_ge;

wire [1:0] cnt5_bai;
wire [3:0] cnt5_shi;
wire [3:0] cnt5_ge;

reg start_flag;
reg pause_flag;

reg [6:0]	current_state, next_state;
parameter	IDLE = 7'd00,		
					S01 = 7'd01,				
			   	S02 = 7'd02,			
					S03 = 7'd03,			
			   	S04 = 7'd04,
			   	S05 = 7'd05,
					S_CHECK = 7'd125;
				
counter_1s counter_1s(
		.clk					(clk),
		.reset_n				(reset_n),
		.clk_1s				(clk_1s)
); 

Control Control(
		.clk 					(clk),
		.reset_n 			(reset_n),
	 
		.add_set 			(add_set),
		.start_set			(start_set),
	 
		.stop_set			(stop_set),
		
		.add_set_r			(add_set_r),
		.start_set_r		(start_set_r),
	 
		.stop_set_r			(stop_set_r)
);

BinToDec BinToDec_cnt1(
		.clk					(clk),
		.reset_n				(reset_n),
		.bin					(cnt1),
		.one					(cnt1_ge),
		.ten					(cnt1_shi),
		.hun					(cnt1_bai)
);

BinToDec BinToDec_cnt2(
		.clk					(clk),
		.reset_n				(reset_n),
		.bin					(cnt2),
		.one					(cnt2_ge),
		.ten					(cnt2_shi),
		.hun					(cnt2_bai)
);

BinToDec BinToDec_cnt3(
		.clk					(clk),
		.reset_n				(reset_n),
		.bin					(cnt3),
		.one					(cnt3_ge),
		.ten					(cnt3_shi),
		.hun					(cnt3_bai)
);

BinToDec BinToDec_cnt4(
		.clk					(clk),
		.reset_n				(reset_n),
		.bin					(cnt4),
		.one					(cnt4_ge),
		.ten					(cnt4_shi),
		.hun					(cnt4_bai)
);

BinToDec BinToDec_cnt5(
		.clk					(clk),
		.reset_n				(reset_n),
		.bin					(cnt5),
		.one					(cnt5_ge),
		.ten					(cnt5_shi),
		.hun					(cnt5_bai)
);

always@(posedge clk or negedge reset_n) begin
	if(~reset_n) begin
		start_flag <= 1'b0;
		pause_flag <= 1'b0;
	end
	else
		if(start_set_r == 1'b1) begin
			start_flag <= 1'b1;
		end
		
		else if(stop_set_r == 1'b1) begin
			pause_flag <= ~pause_flag;
		end
		
		else if(looptimes == 4'b0) begin
			start_flag <= 1'b0;
		end 
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		cnt <= 8'd129;
	else
		if(start_flag == 1'b1) begin
			if(clk_1s == 1'b1) begin
				cnt <= cnt - 1'b1;
				if(cnt == 8'd0)
					cnt <= 8'd129;
			end
		end
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		current_state <= IDLE;
	else
		current_state <= next_state;
end

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