FPGA中1位全加器的实现

最新推荐文章于 2024-08-04 14:17:52 发布

jk_101

最新推荐文章于 2024-08-04 14:17:52 发布

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分类专栏： FPGA

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1位全加器

1.调用门元件

module full_add(a,b,din,sum,cout);

    input a,b,cin;
    output sum,cout;

    wire s1,m1,m2,m3;

    and (m1,a,b);
        (m2,b,cin);
        (m3,a,cin);

    xor (s1,a,b);
        (sum,s1,cin);
        
    or  (cout,m1,m2,m3);
endmodule

2.数据流描述

module full_add(a,b,cin,sum,cout);

    input a,b,cin;
    output sum,cout;

    assign sum = a^b^cin;

    assign cout = (a&b)|(b&cin)|(cin&a)
endmodule

3.行为描述

module full_add(a,b,cin,sum,cout);

    input a,b,cin;
    output sum,cout;

    assign {cout,sum} = a+b+cin;
endmodule

或者

module full_add(a,b,cin,sum,cout);

    input a,b,cin;
    output sum,cout;

    reg sum,cout;

    reg m1,m2,m3;
    
    always @(a or b or cin)
        begin
            sum = (a^b)^cin;
            m1 = a&b;
            m2 = b&cin;
            m3 = a&cin;
            cout = (m1|m2)|m3;
        end
endmodule

4.混合描述

module full_add(a,b,cin,sum,cout);

    input a,b,cin;
    output sum,cout;

    reg cout,m1,m2,m3;

    wire s1;

    xor x1(s1,a,b);

always @(a or b or cin)
    begin
        m1 = a&b;
        m2 = b&cin;
        m3 = a&cin;
        cout = (m1|m2)|m3;
    end

assign sum = s1^cin;

endmodule