verilog定义一个１Khz的闪灯程序

每一个always都会有一个end,同时也定义了启动条件，比如posedge clk50m（posedge 表示THR的上升沿到来时）
///landy
(mark_debug = “true”) reg [31:0] cnt; //定义一个计数器计时
localparam F_K_1 = 50_000;
reg [15:0] cnt_1k;
(mark_debug = “true”)reg clk_1khz;
always@(posedge clk50m)
begin
if(rst) begin
{clk_1khz, cnt_1k} <= {1’d0, 16’d0};
end
else
begin
cnt_1k <= (cnt_1k < F_K_1 - 1) ? cnt_1k + 16’d1 : 16’d0;
case(cnt_1k)
F_K_1 - 16’d2 : clk_1khz <= 1’d1;
default: clk_1khz <= 1’d0;
endcase
end
end
always@(posedge clk50m)
begin
if(rst)
　begin
　{leds_tri_o, cnt} <= {4’h0, 32’d0}; //复位置0计
　end
else if(clk_1khz)
begin
cnt<= cnt +1 ;
//leds_tri_o <=(cnt >= 500) ? 4’h0: 4’hF;
tx_data<=8’h1F;
//new_tx_data<=8’h1F;
fifo_wr_en <= 1’d1;
if(cnt >= 1000) cnt <= 0;
end
else fifo_wr_en <= 1’d0;
end