Verilog 的always块里面的敏感列表里的信号为电平型

always的敏感列表里面是电平敏感型，只要电平满足条件，就会输出一次测量结果。如下代码当rst为低电平时，一直满足(!rst）一直为真，输出out一直为1。

`timescale 1ns/1ps;
module top(

input rst,
input [1:0]sel,
output reg out
);

always @ (rst or sel)begin
    if (!rst)
    out = 1;
    else if (sel!= 0)
    out = 0;
    else 
    out =0;
end

endmodule

`timescale 1ns/1ns
module tb_dianping();
reg rst;
reg [1:0]sel;
wire out;

initial begin
rst = 1'b1;
sel = 2'd0;
#200 rst = 1'b0;
#50 sel =2'd1;
#70 sel = 2'd2;
#15 sel = 2'd3;
end

 top top_u(
.rst(rst),
.sel(sel),
.out(out)
);

endmodule