module leding(clk,q,clk6m,outen,t1us);
input clk;
input outen;
output t1us;
output q;
output clk6m;
reg t1us;
reg q;
reg[23:0] counter;
reg clk6m;
always@(posedge clk )
begin
counter<=counter+1'b1;
q<=counter[23];
if(outen==1'b1)
begin
clk6m<=counter[2];
t1us<=counter[4];
end
else
begin
clk6m<=1'b0;
t1us<=1'b0;
end
end
endmodule
ep240--leding
最新推荐文章于 2024-08-27 18:37:18 发布