该专栏为热销专栏榜 第19名回到首页：2023 数字IC设计秋招复盘——数十家公司笔试题、面试实录
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题目背景
- 笔试时间：2022.08.28
- 应聘岗位：数字前端设计/验证工程师
- 笔试时长：60min
- 笔试平台：nowcoder牛客网
- 题目类型：企业知识题（2道）、智力题（5题）、技术多选题（5道）、技术单选题（10道）、技术问答题（6道）
题目评价
- 难易程度：★★★☆☆
- 知识覆盖：★★☆☆☆
- 超纲范围：★☆☆☆☆
- 值得一刷：★★★☆☆
说明：芯原的笔试比较奇葩，企业价值观也比较独特，投递必须观看宣讲会，并且比试中也需要考宣讲会提到的企业价值等。所以有 企业知识题（2道）。
文章目录
- 第一部分：企业知识题，建议1分钟作答|5分
- 第二部分：智力题，建议14分钟作答| 4分
- 第三部分：技术多选题，建议10分钟作答| 3分
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- 1 Which of the following statements are TRUE about "Single-port SRAM, Dual-port SRAM and Two-port SRAM"?
- 2 Which of the following statements are TRUE about Timing?
- 3 Which of the following statements are TRUE about low power design?
- 4 In system verilog, which of the following methods can be used by queue?
- 5 Which of the following statements are TRUE about DFT technical?
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- 第四部分：技术单选题，建议10分钟作答| 3分
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- 1 Which is not TRUE about the synchronous clock and asynchronous clock?
- 2 If you need to develop a monitor to sample data from DUT's interface, you will write the sample code to which UVM phase?
- 3 Please choose the logic diagram inside ? block according to the timing waveform ()
- 4 Which of the following options has the correct value of cr?
- 5 5. An asynchronous FIFO with 8bit data width, the FIFO write clock is 100MHz, the read clock is 95MHz, if a data packet size is 4K bit, assuming the inter packet time(the time between two packets) is enough, to avoid data missing, what is the minimum depth of the FIFO? ( )
- 6 If only MUX2 is allowed, how many MUX2 is needed at least to implement XOR2 logic?
- 7 Which one is the correct weight distribution of src and dst?
- 8 Which interface below is not belong to SERDES?
- 9 We have several task in module tb. Which print is the expect result ?
- 10 When a circuit is implemented by Verilog code, which level code is most used?
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- 第五部分:技术问答题，建议25分钟作答
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- 1 Read below timing report and answer question. (8 scores)
- 2 Please write Verilog code to implement rising-edge detect using asynchronous reset and synchronous reset. The input signal is: sig_a, output signal is: sig_b. (6 scores)
- 3 AS we know, handshake is a way to make sure data correctly transter through pipline. It constructs of valid, ready/acknowledge signal and data to be tansferred. Please design one handshake delay method, in which combinational logic of valid and acknowledge signal are parted by flip-flop respectively to improve timning. (6 scores)
- 4 What is RAW (read-after-write hazard) in CPU? (1 scores)
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