数字IC设计/FPGA笔试题探讨-芯原

关于2022芯原芯片设计 笔试题分析和讨论_by_小秦同学的博客-CSDN博客_芯片设计笔试题文章中提及的“Which of the following statements are TRUE about Synthesis?”，参照Synthesis Methodology & Netlist Qualification

Synthesis Inputs and Outputs

Input

1. Timing library (.lib or .db)
2. Physical Library (lef, Milkyway)
3. SDC
4. RTL
5. DEF (For Physical aware Synthesis)
6. TLU+(Synopsys), Qrc(cadence) file
7. UPF

Output

1. Netlist
2. UPF
3. SDC
4. DEF
5. Reports

Goal of Synthesis

1. Logic optimization with good QoR