VESA--1080P时序代码

视频信号时序驱动说明--VESA V1.0.13_独木舟216的博客-CSDN博客目录1、屏幕显示原理：2、 驱动显示器：3、VESA时序说明--1080P1、屏幕显示原理：屏幕是一个微型宇宙，有自己的空间和时间规则。远远望去，屏幕上呈现出平滑的二维图像。 近距离观察，它分解成许多独立的原色块：红色、绿色和蓝色。 我们将这种复杂性隐藏在像素的抽象概念背后：我们可以控制的屏幕的最小部分。 典型的高清屏幕是 1920 x 1080：总共 200 万像素。即使是古老的 640x480 VGA 屏幕也有超过 300,0...https://blog.csdn.net/m0_37779673/article/details/1198506451080P时序图：

 

代码：

module DispTimGen#(
    parameter  HOR_BW        = 12                       ,
    parameter  VER_BW        = 11                       ,
//              1080P @ 60Hz 参数值
    parameter  H_TOTAL       = 2200                     ,
    parameter  HS_START      = 44                       ,
    parameter  HDE_START     = 192                      ,
    parameter  HDE_END       = 2112                     ,
    parameter  V_TOTAL       = 1125                     ,
    parameter  VS_START      = 5                        ,
    parameter  VDE_START     = 41                       ,
    parameter  VDE_END       = 1121         
)(
//===================================    INPUT    =====================================
    input                               InClk               ,
    input                               InLocked            ,
//===================================    OUTPUT    ====================================
    output    reg                       OutVs             ,
    output    reg                       OutHs             ,
    output    reg                       OutDe             
);

//localparam      

//======================================================================================
//reg    
reg  [               HOR_BW-1:0 ]       HsCnt    =  'd0  ;
reg                                     HsCntEnd =  'b0  ;
reg                                     DispHsEn =  'd0  ;
reg  [               VER_BW-1:0 ]       VsCnt    =  'd0  ;
reg                                     VsCntEnd =  'b0  ;
reg                                     VsEnd    =  'd0  ;
reg                                     DispVsEn =  'd0  ;
reg                                     Rst      =  'd0  ;
always @ (posedge InClk or negedge InLocked) begin //产生Timing计数复位信号
    if( ! InLocked )
        Rst <= 1'b1 ;
    else
        Rst <= 1'b0 ;
end
//======================================================================================
//              HSync Cnt  
always @ ( posedge InClk )begin
    if(HsCnt[HOR_BW-1:0] == (H_TOTAL - 'd2))
        HsCntEnd <= 1'd1;
    else 
        HsCntEnd <= 1'd0;
end
always @( posedge InClk )begin
    if( Rst )
        HsCnt[HOR_BW-1:0]           <= 'd0                     ;
    else begin
        if( HsCntEnd ) 
            HsCnt[HOR_BW-1:0]       <= 'd0                      ;
        else  
            HsCnt[HOR_BW-1:0]       <= HsCnt + 1'b1              ;
    end
end
//======================================================================================
//              VSync Cnt
always @ ( posedge InClk )begin
    if( VsCnt[VER_BW-1:0] == (V_TOTAL - 1'b1) )
        VsCntEnd <= 1'd1;
    else
        VsCntEnd <= 1'd0;
end

always @ (posedge InClk)begin
    if( Rst )
        VsCnt[VER_BW-1:0]       <= 'd0                      ;
    else begin
        if( HsCntEnd & VsCntEnd )
            VsCnt[VER_BW-1:0]   <= 'd0                      ;
        else if ( HsCntEnd )
            VsCnt[VER_BW-1:0]   <= VsCnt[VER_BW-1:0] + 1'b1 ;
    end
end
//======================================================================================
//                          Hs      OUTPUT Logic
always @( posedge InClk ) begin
    if( Rst ) 
        OutHs                       <= 1'b1         ;
    else begin
        if ( HsCnt[HOR_BW-1:0] == 'd0 ) 
            OutHs                   <= 1'b0         ;                
        // HsDeStart - HsSyncStart
        else if ( HsCnt[HOR_BW-1:0] == HS_START - 'd1 )
            OutHs                   <= 1'b1         ;
    end 
end
//======================================================================================
//                         Vs      OUTPUT Logic
always @( posedge InClk )begin
    if( (VsCnt[VER_BW-1:0] == VS_START - 'd1) & HsCntEnd )
        VsEnd   <=  'd1     ;
    else 
        VsEnd   <=  'd0     ;
end

always @(posedge InClk ) begin
    if( Rst ) begin
        OutVs                       <= 1'b1         ;
    end else begin
        if( VsCnt[VER_BW-1:0] == 'd0 ) 
            OutVs                   <= 1'b0         ;
        else if( VsEnd )
            OutVs                   <= 1'b1         ;
    end
end
//                         De      OUTPUT Logic
always @ (posedge InClk)begin
    DispHsEn <= ((HsCnt[HOR_BW-1:0] >= HDE_START) & (HsCnt[HOR_BW-1:0] < HDE_END));
end

always @ (posedge InClk) begin
    DispVsEn <= ((VsCnt[VER_BW-1:0] >= VDE_START) & (VsCnt[VER_BW-1:0] < VDE_END));
end

always @(posedge InClk ) begin
    if( Rst ) begin
        OutDe       <= 1'b1                     ;
    end else begin
        OutDe       <= (DispVsEn & DispHsEn)    ;
    end
end


endmodule