从零开始的FPGA学习9-状态机实例

状态图

Mealy 型有限状态机

module lab( 
    input clk, 
    input rst, 
    input A, 
    output reg F, 
    output reg G 
    ); 
    reg [3:0] state ; 
    parameter Idle = 4'b1000; 
    parameter Start = 4'b0100; 
    parameter Stop = 4'b0010; 
    parameter Clear = 4'b0001;  
    always @(posedge clk) 
        begin  
            if (!rst) 
                begin  
                    state <= Idle; 
                    F<=0;  
                    G<=0;  
                end  
            else  
                begin 
                    case (state) 
                        Idle:  
                            begin 
                                if (A) 
                                    begin  
                                        state <= Start; 
                                        G<=0;  
                                    end  
                                else  
                                    state <= Idle;  
                            end  
                        Start: 
                            begin 
                                if (!A) 
                                    state <= Stop;  
                                else  
                                    state <= Start; 
                            end  
                        Stop: 
                            begin 
                                if (A) 
                                    begin  
                                        state <= Clear; 
                                        F <= 1; 
                                    end 
                                else  
                                    state <= Stop; 
                            end  
                        Clear:  
                            begin  
                                if (!A) 
                                    begin 
                                        state <=Idle;  
                                        F<=0;  
                                        G<=1;  
                                    end  
                                else 
                                    state <= Clear; 
                            end 
                        default:  
                            state <=Idle; 
                    endcase  
                end 
        end 
endmodule