Fsm hdlc

 

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    
    parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7;
    reg [2:0] state,next_state;
    
    always@(posedge clk) begin
        if(reset)
            state<=S0;
        else
            state<=next_state;
    end
    
    //Mealy
    always@(*) begin 
        case(state)
            S0: next_state = in?S1:S0;
            S1: next_state = in?S2:S0;
            S2: next_state = in?S3:S0;
            S3: next_state = in?S4:S0;
            S4: next_state = in?S5:S0;
            S5: next_state = in?S6:S0;
            S6: next_state = in?S7:S0;
 			S7: next_state = in?S7:S0;
        endcase
    end
    
    always@(posedge clk) begin
        disc <= (~reset)&(~in)&(state==S5);
        flag <= (~reset)&(~in)&(state==S6);
        err <= (~reset)&in&state[1]&state[2];
    end


endmodule

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    
    parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7,S8=8,S9=9;
    reg [3:0] state,next_state;
    
    always@(posedge clk) begin
        if(reset)
            state<=S0;
        else
            state<=next_state;
    end
    
    //Moore
    always@(*) begin
        case(state)
            S0: next_state = in?S1:S0;
            S1: next_state = in?S2:S0;
            S2: next_state = in?S3:S0;
            S3: next_state = in?S4:S0;
            S4: next_state = in?S5:S0;
            S5: next_state = in?S7:S6;
            S6: next_state = in?S1:S0;
 			S7: next_state = in?S9:S8;
            S8: next_state = in?S1:S0;
            S9: next_state = in?S9:S0;    
            default:next_state = S0;
        endcase
    end
    
    assign disc = (state==S6);
    assign flag = (state==S8);
    assign err = (state==S9);

endmodule

 

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    
    parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7,S8=8,S9=9;
    reg [3:0] state,next_state;
    reg [2:0] counter;
    
    always@(posedge clk) begin
        if(reset)
            state<=S0;
        else
            state<=next_state;
    end
    
    always@(posedge clk) begin
        if(state==S1)
            counter<=counter+1'b1;
        else
            counter<=0;
    end
    //Moore改进 将S1,S2,S3,S4合并，使用计数器,可省略一些状态
    always@(*) begin
        case(state)
            S0: next_state = in?S1:S0;
            S1: next_state = in?((counter==3)?S5:S1):S0;
       
            S5: next_state = in?S7:S6;
            S6: next_state = in?S1:S0;
 			S7: next_state = in?S9:S8;
            S8: next_state = in?S1:S0;
            S9: next_state = in?S9:S0;    
            default:next_state = S0;
        endcase
    end
    
    assign disc = (state==S6);
    assign flag = (state==S8);
    assign err = (state==S9);

endmodule