module top_module (
input clk,
input reset,
output [9:0] q);
always@(posedge clk) begin
if(reset)
q<=0;
else if(q==999)
q<=0;
else
q<=q+1'b1;
end
endmodule
Exams/review2015 count1k
最新推荐文章于 2024-09-14 22:33:48 发布