Verilog学习之Vector4:Replication operator

The concatenation operator allowed concatenating together vectors to form a larger vector. But sometimes you want the same thing concatenated together many times, and it is still tedious to do something like assign a = {b,b,b,b,b,b};. The replication operator allows repeating a vector and concatenating them together:

{num{vector}}

num必须是常数，且被复制num次

连接运算符允许将向量连接在一起以形成更大的向量。但有时您希望将同一事物多次连接在一起，并且执行诸如 assign a = {b,b,b,b,b,b}; 之类的操作仍然很乏味。复制运算符允许重复一个向量并将它们连接在一起：

This replicates vector by num times. num must be a constant. Both sets of braces are required.

Examples:两个大括号都是必须的

{5{1'b1}}           // 5'b11111 (or 5'd31 or 5'h1f)
{2{a,b,c}}          // The same as {a,b,c,a,b,c}
{3'd5, {2{3'd6}}}   // 9'b101_110_110. It's a concatenation of 101 with
                    // the second vector, which is two copies of 3'b110.

 

A Bit of Practice

One common place to see a replication operator is when sign-extending a smaller number to a larger one, while preserving its signed value. This is done by replicating the sign bit (the most significant bit) of the smaller number to the left. For example, sign-extending 4'b0101 (5) to 8 bits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8 bits results in 8'b11111101 (-3).

Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.

看到复制运算符的一个常见地方是，将较小的数字符号扩展为较大的数字，同时保留其符号值。这是通过将较小数字的符号位（最高有效位）复制到左侧来完成的。例如，将 4'b0101 (5) 符号扩展至 8 位会产生 8'b00000101 (5)，而将 4'b1101 (-3) 符号扩展至 8 位会产生 8'b11111101 (-3)。构建一个将 8 位数字符号扩展为 32 位的电路。这需要连接 24 个符号位副本（即复制 bit[7] 24 次），然后是 8 位数字本身。

重复操作符的应用场景之一是在有符号数的扩展。有符号数的扩展是将符号位填充待扩展的比特。比如要将 4bit 的 4'b0101 有符号数扩展为 8bit ,0 是符号位，那么扩展之后为 8'b0000 0101.

现在要求构建一个电路，将一个 8bit 有符号数扩展为 32bit 数。

Module Declaration

module top_module (
    input [7:0] in,
    output [31:0] out );

module top_module (
    input [7:0] in,
    output [31:0] out );//

    // assign out = { replicate-sign-bit , the-input };
    assign out = {{24{in[7]}},in};

endmodule