20210329HDLBits学习笔记：Verilog language - vectors

vector reversal1:

assign out[7:0] = in[0:7]; does not work because Verilog does not allow vector bit ordering to be flipped.
因此只能想到按bit使用连接符

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule

Replication operator:

将有符号信号扩展，高位复制信号的符号位。

module top_module (
	input [7:0] in,
	output [31:0] out
);

	// Concatenate two things together:
	// 1: {in[7]} repeated 24 times (24 bits)
	// 2: in[7:0] (8 bits)
	assign out = { {24{in[7]}}, in };
	
endmodule

注意连接符本身就是两层{}。