三段式状态机

`timescale 1ns / 1ps

module water_sell(
	input wire	clk	,
	input wire  rst_n	,
	input wire  half	,
	input wire  one	,
	
	output reg water	,
	output reg change
);
	parameter	ZERO 		= 5'b00001;
	parameter	HALF 		= 5'b00010;
	parameter	ONE  		= 5'b00100;
	parameter	ONE_HALF    = 5'b01000;
	parameter	TWO 		= 5'b10000;
	
	reg 	[4:0]	            c_state;
	reg 	[4:0]	            n_state;

	always @(posedge clk, negedge rst_n)
	begin
		if(rst_n == 1'b0)
			c_state <= ZERO;
		else
			c_state <= n_state;
	end

	always @(*)
	begin
		case(c_state)
			ZERO	: begin
						if(half)
							n_state = HALF;
						else if(one)
							n_state = ONE;
						else
							n_state = ZERO;
					  end
			HALF	: begin
						if(half)
							n_state = ONE;
						else if(one)
							n_state = ONE_HALF;
						else
							n_state = HALF;
					  end
			ONE	: begin
						if(half)
							n_state = ONE_HALF;
						else if(one)
							n_state = TWO;
						else
							n_state = ONE;
					  end
			ONE_HALF:begin
						if(half)
							n_state = TWO;
						else if(one)
							n_state = ZERO;
						else
							n_state = ONE_HALF;
					   end
			TWO	: begin
						if(half || one)
							n_state = ZERO;
						else
							n_state = TWO;
					  end
			default : n_state = ZERO;
		endcase
	end
	
	
	always @(posedge clk, negedge rst_n)
	begin
		if(rst_n == 1'b0)
			water <= 1'b0;
		else
		 case(c_state)
			ZERO : water <= 1'b0;
			HALF : water <= 1'b0;
			ONE : water <= 1'b0;
			ONE_HALF : begin
							if(one)	    water <= 1'b1;
							else		water <= 1'b0;
						  end
			TWO : 	  begin
							if(one || half)      water <= 1'b1;
							else		   	     water <= 1'b0;
						  end
			default: ;
		endcase
	end
	
	always @(posedge clk, negedge rst_n)
	begin
		if(rst_n == 1'b0)
			change <= 1'b0;
		else if(c_state == TWO && one)
			change <= 1'b1;
		else
			change <= 1'b0;
	end
	
endmodule