HDLbits——building larger circuits

building larger circuits

1 Exams/review2015 count1k

module top_module (
    input clk,
    input reset,
    output [9:0] q);
    always@(posedge clk) begin
        if (reset)
            q<=10'b0;
        else if(q<=10'd998)
            q<=q+1'b1;
        else if(q==10'd999)  //d是十进制
            q<=10'b0;
        else
            q<=q;
    end
endmodule

2 Exams/review2015 shiftcount

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);

    always@(posedge clk) begin
        if (shift_ena)
            q<={q[2:0],data};
        else if(count_ena)
            q<=q-1'b1;
            
    end
endmodule

3 Exams/review2015 fsmseq

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    
    parameter S0=0, S1=1,S2=2, S3=3,END=4; 
    reg [2:0] state, next_state;
    always @(*) begin
        case(state) 
            S0:next_state=data?S1:S0;
            S1:next_state=data?S2:S0;
            S2:next_state=data?S2:S3;// data为1时， S2还是回到S2
            S3:next_state=data?END:S0;
            END:next_state=END;
        endcase
    end
    always @(posedge clk) begin
        if(reset) 
            state<=S0;
        else 
            state<=next_state;
    end
    assign start_shifting= (state==END)?1'b1:1'b0;

endmodule

4 Exams/review2015 fsmshift

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    reg[3:0] state,next_state;
    parameter IDLE=0,S0=1,HIGN1=2,HIGN2=3,HIGN3=4,HIGN4=5,LOW=6;
    
    
    always@(posedge clk) begin
        state<=next_state;
    end
    always@(*) begin
        case(state)
            IDLE:next_state=S0;
            S0:next_state=reset?HIGN1:S0;
            HIGN1:next_state=HIGN2;
            HIGN2:next_state=HIGN3;
            HIGN3:next_state=HIGN4;
            HIGN4:next_state=LOW;
            LOW:next_state=IDLE;
            default:next_state=IDLE;
        endcase
    end
    assign shift_ena=(state==HIGN1)||(state==HIGN2)||(state==HIGN3)||(state==HIGN4);
endmodule

5 Exams/review2015 fsm

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    
    reg [3:0] state,next_state;
    parameter data1=4'd1,data2=4'd2,data3=4'd3,data4=4'd4,
               shift1=4'd5,shift2=4'd6,shift3=4'd7,shift4=4'd8,
                cout1=4'd9,endcout1=4'd10;
    
    always@(posedge clk)begin
        if(reset)
            state<=data1;
        else
            state<=next_state;
    end
    always@(*) begin
        case(state)
            data1:next_state=data?data2:data1;
            data2:next_state=data?data3:data1;
            data3:next_state=data?data3:data4;
            data4:next_state=data?shift1:data1;
            shift1:next_state=shift2;
            shift2:next_state=shift3;
            shift3:next_state=shift4;
            shift4:next_state=cout1;
            cout1:next_state=done_counting?endcout1:cout1;
            endcout1:next_state=ack?data1:endcout1;
            default:next_state=data1;
        endcase
        
    end
    assign shift_ena=((state==shift1)||(state==shift2)||(state==shift3)||(state==shift4));
    assign counting=(state==cout1);
    assign done=(state==endcout1);

endmodule

6

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    
    reg [3:0] state,next_state;
    parameter data1=4'd1,data2=4'd2,data3=4'd3,data4=4'd4,
               shift1=4'd5,shift2=4'd6,shift3=4'd7,shift4=4'd8,
                cout1=4'd9,endcout1=4'd10;
    
    always@(posedge clk)begin
        if(reset)
            state<=data1;
        else
            state<=next_state;
    end
    always@(*) begin
        case(state)
            data1:next_state=data?data2:data1;
            data2:next_state=data?data3:data1;
            data3:next_state=data?data3:data4;
            data4:next_state=data?shift1:data1;
            shift1:next_state=shift2;
            shift2:next_state=shift3;
            shift3:next_state=shift4;
            shift4:next_state=cout1;
            cout1:next_state=done_counting?endcout1:cout1;
            endcout1:next_state=ack?data1:endcout1;
            default:next_state=data1;
        endcase
        
    end
    wire shift_ena;
    assign shift_ena=((state==shift1)||(state==shift2)||(state==shift3)||(state==shift4));
    
    assign counting=(state==cout1);
    assign done=(state==endcout1);
    
    wire done_counting;
    assign done_counting=(count==4'd0)&&(cnt==10'd0);//当count等于0时，需要确定cnt也为0，因为题中是delay+1，在代码中当count=0时仍计数减1
    
    always@(posedge clk) begin
        if (reset)
            count<=4'd0;
        else if(shift_ena)
            count<={count[2:0],data};
        else if(counting)
            count<=(cnt==10'd0)?count-4'b1:count;//每个delay（count）都要在cnt计数100次,
        else
            count<=count;

    end
    
    //cout 1000
    reg [9:0] cnt;
    always@(posedge clk) begin
        if (reset)
            cnt<=10'd999;
        else if(counting)
            cnt<=(cnt==10'd0)?10'd999:(cnt-10'd1);//减计数器
        else
            cnt<=10'd999;

    end

endmodule

7 Exams/review2015 fsmonehot

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
); //

    // You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
    parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;
    assign B3_next = state[B2];
    assign S_next = (state[S1]& ~d) |(state[S110]& ~d)|(state[S]& ~d)|(state[Wait]& ack);
    assign S1_next = state[S]&d;
    assign Count_next=state[B3]|(state[Count]& (~done_counting));
    assign Wait_next=(state[Wait]& ~ack)|(state[Count] & done_counting);
    assign counting= state[Count];
    assign done=state[Wait];
    assign shift_ena= state[B0]|state[B1]|state[B2]|state[B3];
    // etc.

endmodule