·以7分频为例,可通过更改N来实现任意奇数分频
时序分析:
(通过Visio绘制,若需时序库可在我的资源处下载)
RTL代码:
module dev_7freq (
input sys_clk,
input sys_rst_n,
output clk_7d
);
parameter N = 7;
reg [2:0] cnt0;
reg [2:0] cnt1;
reg clk0,clk1;
// 以N-1计数器为状态,用于生成 clk0和clk1
always @(posedge sys_clk) begin
if (!sys_rst_n)
cnt0 <= 3'd0;
else if (cnt0 == N-1)
cnt0 <= 3'd0;
else
cnt0 <= cnt0 + 3'd1;
end
always @(negedge sys_clk) begin
if (!sys_rst_n)
cnt1 <= 3'd0;
else if (cnt1 == N-1)
cnt1 <= 3'd0;
else
cnt1 <= cnt0 + 3'd1;
end
// 得到clk0 和 clk1
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
clk0 <= 1'd0;
else if (cnt0 <= (N-3)/2 )
clk0 <= 1'd1;
else
clk0 <= 1'd0;
end
always @(negedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
clk1 <= 1'd0;
else if (cnt0 <= (N-3)/2 )
clk1 <= 1'd1;
else
clk1 <= 1'd0;
end
assign clk_7d = clk0 || clk1;
endmodule
TB:
`timescale 1ns/1ns
module dev_7freq_tb();
reg sys_clk;
reg sys_rst_n;
wire clk_7d;
initial begin
sys_clk = 1'b0;
sys_rst_n = 1'b0;
# 20 sys_rst_n = 1'b1;
end
always # 10 sys_clk = ~ sys_clk;
dev_7freq u1(
sys_clk,
sys_rst_n,
clk_7d
);
endmodule
Modelsim仿真:
由于sys_clk初始状态与时序分析图的不一样,所以仿真时序有所不同。