仲裁器电路

要求：

1) 最近处理过的信号源，优先级降为最低

2）优先级顺序：信号源0 > 信号源1 > 信号源2 > 信号源3

第一次实现：

 RTL代码：

module arbiter(
	input en,
	input [3:0] sig_now,
	output reg [3:0] sig_last,
	output reg [3:0] out
);

// sig_now为当前信号源，sig_last为上次处理的信号源情况
// 信号源0对应 sig_now[0]
// 高电平表示信号源被处理


always @(*) begin
	if (en)
		sig_last = 4'b0000;
	else begin
		casez(sig_last)
		4'b0001: begin
			casez (sig_now)
			4'b0001: begin
				out = 4'b0001;
				sig_last = out;   // 1
				end
			4'bzz1z: begin
				out = 4'b0010;
				sig_last = out;   // 8
				end
			4'bz10z: begin
				out = 4'b0100;
				sig_last = out;   // 4
				end
			4'b100z: begin
				out = 4'b1000;
				sig_last = out;   // 2
				end
			4'b0000: begin
				out = 4'b0000;
				sig_last = out;   // 1
				end 
			endcase
		end
		
		4'b0010: begin
			casez(sig_now)
			4'bzzz1: begin
				out = 4'b0001;
				sig_last = out;    // 8
				end
			4'b0010: begin
				out = 4'b0010;
				sig_last = out;    // 1
				end
			4'bz1z0: begin
				out = 4'b0100;
				sig_last = out;    // 4
				end
			4'b10z0: begin
				out = 4'b1000;
				sig_last = out;	   // 2
				end
			4'b0000: begin
				out = 4'b0000;
				sig_last = out;    // 1
				end
			endcase
		end
		
		4'b0100: begin
			casez(sig_now)
			4'bzzz1: begin
				out = 4'b0001;
				sig_last = out;
				end
			4'bzz10: begin
				out = 4'b0010;
				sig_last = out;
				end
			4'b0100: begin
				out = 4'b0100;
				sig_last = out;
				end
			4'b1z00: begin
				out = 4'b1000;
				sig_last = out;
				end
			4'b0000: begin
				out = 4'b0000;
				sig_last = out;
				end
			endcase
		end
			
		4'b1000: begin
			casez(sig_now)
			4'bzzz1: begin
				out = 4'b0001;
				sig_last = out;
				end
			4'bzz10: begin
				out = 4'b0010;
				sig_last = out;
				end
			4'bz100: begin
				out = 4'b0100;
				sig_last = out;
				end
			4'b1000: begin
				out = 4'b1000;
				sig_last = out;
				end
			4'b0000: begin
				out = 4'b0000;
				sig_last = out;
				end
			endcase
		end	
		
		default: begin
			casez(sig_now)
			4'bzzz1: begin
				out = 4'b0001;
				sig_last = out;
				end
			4'bzz10: begin
				out = 4'b0010;
				sig_last = out;
				end
			4'bz100: begin
				out = 4'b0100;
				sig_last = out;
				end
			4'b1000: begin
				out = 4'b1000;
				sig_last = out;
				end
			4'b0000: begin
				out = 4'b0000;
				sig_last = out;
				end
			endcase
		end
		endcase
	end
end


endmodule

TB:

`timescale 1ns/1ns

module arbiter_tb();

reg en;
reg [3:0] sig_now;
wire [3:0] sig_last;
wire [3:0] out;

initial begin
	en = 1'b1;
	# 20 en = 1'b0;
	# 20 sig_now = 4'b0001;
	# 20 sig_now = 4'b0011;
	# 20 sig_now = 4'b0111;
	# 20 sig_now = 4'b1111;
	# 40 $stop;
end

arbiter u1(
	en,
	sig_now,
	sig_last,
	out
);

endmodule

Modelsim仿真:

 图中当前sig_last为下一个sig_now的最近处理情况。