设置静态时序分析环境

setting up clocks, specifying IO timing characteristics, and specifying false paths and multicycle paths

1.Specifying Clocks

create_clock
set_clock_transition：This specification applies only for ideal clocks and is disregarded once the clock trees are built。
set_clock_uncertainty：The uncertainty can be used to model various factors that can reduce the effective clock period. These factors can be the clock jitter and any other pessimism that one may want to include
                       for timing analysis.Note that the clock uncertainty for setup effectively reduces the available clock period by the specified amount as illustrated in Figure 7-7. For hold checks, the clock 
                       uncertainty for hold is used as an additional timing margin that needs to be satisfied。
clock uncertainty 里面对建立时间的检查需要考虑时钟抖动，而对保持时间检查时不需要考虑时钟抖动，知道为啥吗？呵呵。
 
set_clock_latency：There are two types of clock latencies: network latency and source latency. Network latency is the delay from the clock definition point (create_clock) to
                  the clock pin of a flip-flop. Source latency, also called insertion delay, is the delay from the clock source to the clock definition point. Source latency
                  could represent either on-chip or off-chip latency. Figure 7-9 shows both the scenarios. The total clock latency at the clock pin of a flip-flop is the
                  sum of the source and network latencies.
Here are some example commands that specify source and network latencies.
# Specify a network latency (no -source option) of 0.8ns for
# rise, fall, max and min:
set_clock_latency 0.8 [get_clocks CLK_CONFIG]
# Specify a source latency:
set_clock_latency 1.9 -source [get_clocks SYS_CLK]
# Specify a min source latency:
set_clock_latency 0.851 -source -min [get_clocks CFG_CLK]
# Specify a max source latency:
set_clock_latency 1.322 -source -max [get_clocks CFG_CLK]


One important distinction to observe between source and network latency is that once a clock tree is built for a design, the network latency 
can be ignored (assuming set_propagated_clock command is specified). However, the source latency remains even after the clock tree is built.
The network latency is an estimate of the delay of the clock tree prior to clock tree synthesis. After clock tree synthesis, the total clock 
latency from clock source to a clock pin of a flip-flop is the source latency plus the actual delay of the
clock tree from the clock definition point to the flip-flop.


create_generated_clock：A generated clock is a clock derived from a master clock. A master clock is a clock defined using the create_clock specification.For example, if there is a
                        divide-by-3 circuitry for a clock, one would define a generated clock definition at the output of this circuitry.This definition is needed as STA does
                        not know that the clock period has changed at the output of the divide-by logic, and more importantly what the new clock period is.Can a new clock, that is, a 
                        master clock, be defined at the output of the flipflop instead of a generated clock? The answer is yes, that it is indeed possible. However, there are some disadvantages. Defining a 
                        master clock instead of a generated clock creates a new clock domain. This is not a problem in general except that there are more clock domains to deal with 
                        in setting up the constraints for STA. Defining the new clock as a generated clock does not create a new clock domain, and the generated clock is considered
                        to be in phase with its master clock.              Another important difference between a master clock and a generated
                        clock is the notion of clock origin. In a master clock, the origin of the clock is at the point of definition of the master clock. In a generated clock, the
                        clock origin is that of the master clock and not that of the generated clock. This implies that in a clock path report, the start point of a clock path is always the master clock