AXI Slave VIP that control the delay between the AREADY and AVALID

最新推荐文章于 2023-08-29 10:14:37 发布

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最新推荐文章于 2023-08-29 10:14:37 发布

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分类专栏： SystemVerilog 文章标签： delay variables object input function class

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There are two variables in AXI Slave VIP that control the delay between the AREADY and AVALID:

MAX: dw_vip_axi_port_configuration :: m_nMaxDelay = 5000

MIN: m_nAvalidAreadyDelay = 0;

You can set your own Maximum delay in VMM env as below (using configuration):

class axiEnv extends vmm_env; 

    virtual function void gen_cfg() ; 

       super.gen_cfg(); 

       vip_axi_slave_cfg.m_oPortCfg.m_nMaxDelay=3000;

   endfunction : gen_cfg 

endclass

also you can specify the minimum delay in Slave Responseras below (using object member):

task axiSlaveXactor::recv_write();  



    $display("###################################################"); 

    $display($time,,"SLAVE receives a WRITE transaction"); 

    $display("##################################################"); 

    resp_trans.display("SLAVE RECV ::\t"); 

    $display("\n"); 

 

    /* Put the response object into the VIP slave input channel. */ 

    resp_trans.m_nAvalidAreadyDelay =3; 

   o_input_chan.put(resp_trans);  



endtask