AXI 笔记1： 来自SPEC

About the AXI protocol   Is suitable for memory controllers with high initial access latency   Is backward-compatible with AHB and APB interfaces   Separate read and write data channels, that can provide low-cost Direct Memory Access (DMA)   Permits easy addition of register stages to provide timing closure.

AXI Architecture Write data channel information is always treated as buffered, so that the master can perform write transactions without slave acknowledgement of previous write transactions. In most systems, the address channel bandwidth requirement is significantly less than the data channel bandwidth requirement. Such systems can achieve a good balance between system performance and interconnect complexity by using a shared address bus with multiple data buses to enable parallel data transfers.

Signals AWREGION  Permits a single physical interface on a slave to be used for multiple logical interfaces.

Handshake This two-way flow control mechanism means both the master and slave can control the rate that the information moves between master and slave. To prevent a deadlock situation, the dependency rules that exist between the handshake signals must be observed. In addition, there are dependencies between the handshake signals on different channels, and AXI4 defines an additional write response dependency

Address structure A burst must not cross a 4KB address boundary. This prohibition prevents a burst from crossing a boundary between two slaves. It also limits the number of address increments that a slave must support.

Burst length No component can terminate a burst early. However, to reduce the number of data transfers in a write burst, the master can disable further writing by deasserting all the write strobes The ability to break longer bursts into multiple shorter bursts is required for AXI3 compatibility. This ability might also be needed to reduce the impact of longer bursts on the QoS guarantees

Burst type FIXED burst type is used for repeated accesses to the same location such as when loading or emptying         a FIFO INCR  burst type is used for accesses to normal sequential memory. WRAP  burst type is used for cache line accesses.

Peripheral Slave Any access to the peripheral slave that is not part of the IMPLEMENTATION DEFINED method of access must complete, in compliance with the protocol. However, once such an access has been made, there is no requirement that the peripheral slave continues to operate correctly. It is only required to continue to complete further transactions in a protocol compliant manner.

transaction attributes The ARCACHE and AWCACHE signals specify the transaction attributes. They control: • How a transaction progresses through the system. • How any system-level caches handle the transaction.

Cachealbe?