1. getting satrted
module top_module( output one );
assign one = 1;
endmodule
2.output zero
module top_module ( output zero );
assign zero = 1'b0;
endmodule
1. getting satrted
module top_module( output one );
assign one = 1;
endmodule
2.output zero
module top_module ( output zero );
assign zero = 1'b0;
endmodule