Module Hierarchy

1.Modules

module top_module ( input a, input b, output out );
   mod_a instance1(a,b,out);
endmodule

2.Connecting ports by position

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    
    mod_a ins(out1,out2,a,b,c,d);

endmodule

3.Connecting ports by name

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a mod_a(.in1(a),.in2(b),.in3(c),.in4(d),.out1(out1),.out2(out2));

endmodule

4.Three modules

module top_module ( input clk, input d, output q );
    
    wire clk1;
    wire d1,q1,q2,q3;
    
    my_dff my_dff1(.clk(clk),.d(d),.q(q1));
    my_dff my_dff2(.clk(clk),.d(q1),.q(q2));
    my_dff my_dff3(.clk(clk),.d(q2),.q(q));
    
    
endmodule

5.Modules and vectors

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);

    wire [7:0] q1;
    wire [7:0] q2;
    wire [7:0] q3;
    
    my_dff8 my_dff1(.clk(clk),.d(d),.q(q1));
    my_dff8 my_dff2(.clk(clk),.d(q1),.q(q2));
    my_dff8 my_dff3(.clk(clk),.d(q2),.q(q3));
    
    always@(*)
      begin
          case (sel)
              2'b00: q=d;
              2'b01: q=q1;
              2'b10: q=q2;
              2'b11: q=q3;
              default: q=8'b1111_1111;
          endcase
      end
endmodule

6.Adder 1

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
wire [15:0] low;
wire [15:0] high;
wire cout;

add16 add_l0(a[15:0],b[15:0],0,sum[15:0],cout);
    add16 add_h0(a[31:16],b[31:16],0,low);
    add16 add_h1(a[31:16],b[31:16],1,high);

    assign sum[31:16]= cout ? high : low;

endmodule

7.Adder 2

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//

    wire temp_out;
    add16 low(a[15:0],b[15:0],0,sum[15:0],temp_out);
    add16 high(a[31:16],b[31:16],temp_out,sum[31:16]);
    
endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );
    assign {cout,sum}= a+b+cin;
// Full adder module here

endmodule

8.Carry select adder

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire [15:0] low;
    wire [15:0] high;
    wire cout;

    add16 low0(a[15:0],b[15:0],0,sum[15:0],cout);
    add16 h0(a[31:16],b[31:16],0,low);
    add16 h1(a[31:16],b[31:16],1,high);
    
    always@(*)
        begin
    case (cout)
        1'b0: sum={low,sum[15:0]};
        1'b1: sum={high,sum[15:0]};
        default: sum=32'b1111_1111_1111_1111_1111_1111_1111_1111;
    endcase
        end
    
    
endmodule

9.Adder subtractor

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);

    
    wire [31:0] b1;
    wire [15:0] low;
    wire [15:0] high;
    wire cout;
    
    assign b1 = b^{32{sub}};
    
    add16 low0(a[15:0],b1[15:0],sub,sum[15:0],cout);
    add16 h0(a[31:16],b1[31:16],0,low);
    add16 h1(a[31:16],b1[31:16],1,high);
    
    assign  sum[31:16] = cout ? high : low;
    
endmodule