Circuits--Combinational--Basic

1.wire

module top_module (
    input in,
    output out);
 
    wire w;
    assign w=in;
    assign out=w;
endmodule

2.GND

module top_module (
    output out);
    
   assign out=1'b0;
endmodule

3.NOR

module top_module (
    input in1,
    input in2,
    output out);
    
    assign out=~(in1|in2);
 
endmodule

4.Another gate

module top_module (
    input in1,
    input in2,
    output out);
    
    assign out=in1&(~in2);
 
endmodule

5.two gates

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    
    assign out=in3^(~(in1^in2));
 
endmodule

6.More logic gates

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    
    assign out_and=a&b;
    assign out_or=a|b;
    assign out_xor=a^b;
    assign out_nand=~(a&b);
    assign out_nor=~(a|b);
    assign out_xnor=~(a^b);
    assign out_anotb=a&(~b);
                                

endmodule

7.7420 chip

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y=~(p1a&p1b&p1c&p1d);
    assign p2y=~(p2a&p2b&p2c&p2d);


endmodule

8.truth tables

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);

    assign f=(x3&(~x2)&x1)|(~(x3)&x2)|(x2&x1);
endmodule

9.Two-bit equality

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    always @(*)
        begin
            if(A==B) z=1;
            else z=0;
        end
    
endmodule

10.Simple circuit A

module top_module (input x, input y, output z);
    assign z=(x^y)&x;
endmodule

11.simple curcuit B

module top_module ( input x, input y, output z );
    assign z=~(x^y);
endmodule

12.combine circuits A and B

module top_module (input x, input y, output z);  
    wire z1,z2,z3,z4;
    
    assign z1=~(x^y);
    assign z2=(x^y)&x;
    assign z3=~(x^y);
    assign z4=(x^y)&x;
    
    assign z=(z1|z2)^(z3&z4);
 
endmodule

13.Ring or vibrate

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
 
    always@(*)
        begin
            if(ring==1)
                begin
                    if(vibrate_mode) 
                        begin
                            motor=1;
                            ringer=0; 
                        end
                    else
                        begin
                            motor=0; 
                            ringer=1;
                        end
                end
            else
                begin
                    motor=0;
                   ringer=0;
                end
        end
endmodule

14..thermostat

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
    
    assign heater= (mode&too_cold) ? 1:0;
    assign aircon= (~mode&too_hot) ? 1:0;
    assign fan= (heater|aircon|fan_on) ? 1:0;
 
endmodule

15.3-bit population count

module top_module( 
    input [2:0] in,
    output [1:0] out );
    
    integer i;
    always@(*)
        begin
            out=0;
            for(i=0;i<3;i++)
                if(in[i])
                    out=out+1;
        end
 
endmodule

16.Gates and vectors

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    
    integer i;
    always@(*)
        begin
            for(i=0;i<4;i++)
                begin
                    if(i<3)
                        begin
                            out_both[i]= (in[i]&in[i+1]) ? 1:0;
                            out_any[i+1]= (in[i+1]|in[i]) ? 1:0;
                            out_different[i]= (in[i]^in[i+1]) ? 1:0;
                  
                        end
                    if(i==3)
                        out_different[i]=(in[i]^in[i-3]) ? 1:0;
                end
        end
 
endmodule

17.Even longer vectors

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    
     integer i;
    always@(*)
        begin
            for(i=0;i<100;i++)
                begin
                    if(i<99)
                        begin
                            out_both[i]= (in[i]&in[i+1]) ? 1:0;
                            out_any[i+1]= (in[i+1]|in[i]) ? 1:0;
                            out_different[i]= (in[i]^in[i+1]) ? 1:0;
                  
                        end
                    if(i==99)
                        out_different[99]=(in[99]^in[0]) ? 1:0;
                end
        end
 
endmodule