Circuits--Sequential--Registers

1.4-bit shift register

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    
    always@(posedge clk or posedge areset)
        begin
            if(areset)
                q<=4'b0;
            else if(load)
              q<=data;
            else if(ena)
                q<={1'b0,q[3:1]};  //右移一位
            else
                q<=q;
        end

endmodule

2.Left/right rotator

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
    
 
    always@(posedge clk)
        begin
            if(load)
                q<=data;
            else
                begin
                    case(ena)
                        2'b00:	q<=q;
                        2'b01:	q<={q[0],q[99:1]};
                        2'b10:	q<={q[98:0],q[99]};
                        2'b11:	q<=q;          		
                    endcase
                end
        end

endmodule

3.Left / right arithmetic 

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    
    always@(posedge clk)
        begin
            if(load)
                q<=data;
            else if(ena)
                begin
                    case(amount)
                        2'b00:	q<={q[62:0],1'b0}; 
                        2'b01:	q<={q[55:0],8'b0};
                        2'b10:	q<={q[63],q[63:1]};  //保留符号位
                        2'b11:	q<={{8{q[63]}},q[63:8]};
                    endcase
                end
        end

endmodule

4.5-bit LFSR

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
    
    always@(posedge clk)
        begin
            if(reset)
                q<=5'h1;
            else
                begin
                    q[4]<=q[0]^1'b0;
                    q[3]<=q[4];
                    q[2]<=q[3]^q[0];
                    q[1]<=q[2];
                    q[0]<=q[1];
                end
        end

endmodule

5.3-bit 

LFSR

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
 
    wire clk = KEY[0];
    always @(posedge clk)
        begin
            case(KEY[1])
                1'b0:	
                    begin
                        LEDR[0]<=LEDR[2];
                        LEDR[1]<=LEDR[0];
                        LEDR[2]<=LEDR[1]^LEDR[2];
                    end
                1'b1:	
                    begin
                        LEDR[0]<=SW[0];
                        LEDR[1]<=SW[1];
                        LEDR[2]<=SW[2];
                    end
            endcase
        end
endmodule

6.32-bit LFSR

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 
    
    integer i;
    always@(posedge clk)
        begin
            if(reset)
                q<=32'h1;
            else
                begin
                    for(i=0;i<32;i++)
                        begin
                            if(i==0||i==1||i==21) 
                                q[i]<=q[i+1]^q[0];
                            else if(i==31)
                                q[31]<=q[0]^1'b0;
                            else
                                q[i]<=q[i+1];
                        end
                    
                end
            
        end
endmodule

7.shift register_1

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    
    reg [3:0] q;
    
    assign out = q[3];
    always@(posedge clk)
        begin
            if(!resetn)
                q<=0;
            else
                begin                 
                    q<={q[2:0],in};                       
                end
        end
endmodule

8.  shift register_2

module top_module(
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
);
 
    MUXDFF MUXDFF1(
        .clk(KEY[0]),
        .w(KEY[3]),
        .R(SW[3]),
        .E(KEY[1]),
        .L(KEY[2]),
        .Q(LEDR[3])
    );
    
     MUXDFF MUXDFF2(
        .clk(KEY[0]),
        .w(LEDR[3]),
        .R(SW[2]),
        .E(KEY[1]),
        .L(KEY[2]),
        .Q(LEDR[2])
    );
 
     MUXDFF MUXDFF3(
        .clk(KEY[0]),
        .w(LEDR[2]),
        .R(SW[1]),
        .E(KEY[1]),
        .L(KEY[2]),
        .Q(LEDR[1])
    );
 
     MUXDFF MUXDFF4(
        .clk(KEY[0]),
        .w(LEDR[1]),
        .R(SW[0]),
        .E(KEY[1]),
        .L(KEY[2]),
        .Q(LEDR[0])
    );
endmodule
 
    module MUXDFF(
        input clk,
        input w,R,E,L,
        output Q
    );
 
    wire p;
    always @(posedge clk) begin
        case (E)
            1'b0: p=Q;
            1'b1: p=w;
    
        endcase
 
        case (L)
            1'b0: Q=p;
            1'b1: Q=R;
          
        endcase
    end
 
endmodule

9. 3-input 

LUT

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    
    reg [7:0] p;
    always@(posedge clk)
        begin
            if(enable)
                p <= {p[6:0],S};
            else
                p <= p;
        end
    
    assign Z = p[{A,B,C}];
 
endmodule