VHDL棋类竞赛设计（一）

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已于 2022-06-07 18:35:54 修改

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分类专栏： VHDL 文章标签： fpga开发

于 2022-06-07 18:35:07 首次发布

本文链接：https://blog.csdn.net/qq_17018135/article/details/125170882

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这篇文章详细介绍了如何使用VHDL设计一个竞赛计时器，包括50秒规定用时和8秒读秒阶段的计时逻辑，以及模拟落子操作对计时的影响。它还展示了两个独立的计时模块（50秒和8秒）的VHDL代码和测试bench。控制器模块负责协调双方的计时，当一方超时则比赛结束。

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设计要求：
竞赛计时分两个阶段：每方50秒的规定用时和每方每步8秒的读秒。
1．可分别显示甲乙双方规定用时阶段的已用时间和读秒阶段(8秒)的倒计时；
2．设置两路输入模拟双方落子，在规定用时阶段，一路信号有效时会暂停本方计时并继续对方计时，而在读秒倒计时阶段，它用来暂停本方倒计时，并启动对方8秒倒计时；
3. 若其中一方倒计时到零，则用一路输出表示该方超时负，比赛结束

50秒倒计时模块

VHDL：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
    ENTITY cnt50s IS
      PORT (
        clk  : IN    STD_LOGIC;
        cir  : IN    STD_LOGIC; 
        en   : IN    STD_LOGIC;
        co   : OUT   STD_LOGIC;
        sunit   : OUT   STD_LOGIC_VECTOR (3 DOWNTO 0);
        stent   : OUT   STD_LOGIC_VECTOR (3 DOWNTO 0)
      );
    END cnt50s;

    ARCHITECTURE a OF cnt50s IS
      SIGNAL unit : STD_LOGIC_VECTOR (3 DOWNTO 0);
      SIGNAL tent : STD_LOGIC_VECTOR (3 DOWNTO 0);
    BEGIN
      PROCESS (clk, cir, en)
        BEGIN
          IF (cir = '1') THEN 
              co <= '0';
              unit <= "1001";
              tent <= "0100";
          ELSIF (clk'EVENT AND clk = '1' AND en = '1') THEN 
              unit <= unit - 1;
              IF (unit = "0000") THEN 
                  unit <= "1001";
                  tent <= tent - 1;
                  IF (tent = "0000") THEN
                      co <= '1';
                  END IF;
              END IF;
          END IF;

      END PROCESS;
		    sunit <= unit;
          stent <= tent;
 END a;

Testbench：

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY cnt50s_vhd_tst IS
END cnt50s_vhd_tst;
ARCHITECTURE cnt50s_arch OF cnt50s_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL cir : STD_LOGIC;
SIGNAL clk : STD_LOGIC;
SIGNAL co : STD_LOGIC;
SIGNAL en : STD_LOGIC;
SIGNAL stent : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sunit : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT cnt50s
	PORT (
	cir : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	co : OUT STD_LOGIC;
	en : IN STD_LOGIC;
	stent : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	sunit : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END COMPONENT;
BEGIN
	i1 : cnt50s
	PORT MAP (
-- list connections between master ports and signals
	cir => cir,
	clk => clk,
	co => co,
	en => en,
	stent => stent,
	sunit => sunit
	);
init : PROCESS                                               
-- variable declarations                                     
BEGIN   
cir<='1';wait for 30ns;
cir<='0';                                                  
en<='1';wait for  40ns;       -- code that executes only once                      
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
                                     
BEGIN      
                                                   
 clk<='0';wait for 10ns;
 clk<='1';wait for 10ns; 
END PROCESS always;                                          
END cnt50s_arch;

在这里插入图片描述

8秒倒计时模块

VHDL：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
    ENTITY cnt8s IS
      PORT (
        clk  : IN    STD_LOGIC;
        cir  : IN    STD_LOGIC; 
        en   : IN    STD_LOGIC;
        co   : OUT   STD_LOGIC;
        sunit   : OUT   STD_LOGIC_VECTOR (3 DOWNTO 0));

    END cnt8s;

    ARCHITECTURE a OF cnt8s IS
      SIGNAL unit : STD_LOGIC_VECTOR (3 DOWNTO 0);
	
    BEGIN
      PROCESS (clk, cir, en)
        BEGIN
          IF (cir = '1') THEN 
              co <= '0';
              unit <= "0111";
          ELSIF (clk'EVENT AND clk = '1' AND en = '1') THEN 
              unit <= unit - 1;
              IF (unit = "0000") THEN 
                   co <= '1';
                  END IF;
              END IF;

      END PROCESS;
		 sunit <= unit;
 END a;

Testbench：

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY cnt8s_vhd_tst IS
END cnt8s_vhd_tst;
ARCHITECTURE cnt8s_arch OF cnt8s_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL cir : STD_LOGIC;
SIGNAL clk : STD_LOGIC;
SIGNAL co : STD_LOGIC;
SIGNAL en : STD_LOGIC;
SIGNAL sunit : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT cnt8s
	PORT (
	cir : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	co : OUT STD_LOGIC;
	en : IN STD_LOGIC;
	sunit : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END COMPONENT;
BEGIN
	i1 : cnt8s
	PORT MAP (
-- list connections between master ports and signals
	cir => cir,
	clk => clk,
	co => co,
	en => en,
	sunit => sunit
	);
init : PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
cir<='1';wait for 30ns;
cir<='0';                                                  
en<='1';wait for  40ns;        -- code that executes only once                      
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
 clk<='0';wait for 10ns;
 clk<='1';wait for 10ns;                                                      
END PROCESS always;                                          
END cnt8s_arch;

在这里插入图片描述

控制器模块

LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
    ENTITY controler IS
      PORT ( 
        count50a, count8a, count50b, count8b  : IN   STD_LOGIC;
        cr, s                             : IN   STD_LOGIC;
        en50a, en8a, en50b, en8b, cr8a, cr8b  : OUT  STD_LOGIC   
      );
    END controler;

    ARCHITECTURE a OF controler IS
    BEGIN
    PROCESS (s, count50a)
      BEGIN
        IF (s = '0') THEN --s=0乙计时
            en50a <= '0'; 
        ELSIF (count50a = '0') THEN 
            en50a <= '1'; 
        ELSE 
            en50a <= '0';
        END IF;
    END PROCESS;

-- process s, count50a, count8a.
    PROCESS (s, count50a, count8a)
    BEGIN
      IF (count8a = '1') THEN 
          en8a <= '0'; -----------
      ELSIF (count50a = '1' AND s ='1') THEN 
          en8a <= '1'; 
      ELSE
          en8a <= '0';
      END IF;
    END PROCESS;

-- process s, count50b.
    PROCESS (s, count50b)
    BEGIN
    IF (s = '1') THEN --s=1 甲计时
        en50b <= '0'; 
    ELSIF (count50b = '0') THEN 
        en50b <= '1'; 
     ELSE
        en50b <= '0';
     END IF;
    END PROCESS;

-- process s, count50b, count8b
    PROCESS (s, count50b, count8b)
    BEGIN
      IF (count8b = '1') THEN 
          en8b <= '0'; 
      ELSIF (count50b = '1' AND s = '0') THEN 
          en8b <= '1'; 
      ELSE  
          en8b <= '0';
      END IF;
    END PROCESS;

-- process s and cr.
    PROCESS (s, cr)
    BEGIN
    IF (cr = '1') THEN 
        cr8a <= '1'; 
    ELSIF (s = '0') THEN 
        cr8a <= '1'; 
    ELSE 
        cr8a <= '0';
    END IF;
    END PROCESS;

-- process s and cr.
    PROCESS (s,cr)
    BEGIN
      IF (cr = '1') THEN 
          cr8b <= '1'; 
      ELSIF (s = '1') THEN 
          cr8b <= '1'; 
      ELSE 
          cr8b <= '0';
      END IF;
    END PROCESS;
END a;