VHDL棋类竞赛设计（二）

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已于 2022-06-07 18:44:20 修改

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分类专栏： VHDL 文章标签： fpga开发

于 2022-06-07 18:43:53 首次发布

本文链接：https://blog.csdn.net/qq_17018135/article/details/125171112

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本文介绍了使用VHDL在FPGA开发中设计棋类竞赛的警报模块，包括警报功能的实现、顶层文件的结构以及设计的连线图，展示了FPGA在游戏竞赛中的应用。

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警报模块

LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
    ENTITY warn IS
      PORT (
        count8a  : IN    STD_LOGIC;
        count8b  : IN    STD_LOGIC;
        cp       : IN    STD_LOGIC;
        dididi     : OUT   STD_LOGIC;
        a, b     : OUT   STD_LOGIC 
      ); 
    END warn;

    ARCHITECTURE a OF warn IS
    BEGIN
    PROCESS (count8a, count8b)
      BEGIN
        IF (count8a = '1' OR count8b = '1') THEN 
            dididi <= CP;
        ELSE
            dididi <= '0';
        END IF;
    END PROCESS;

-- process count8a, cp.
    PROCESS (count8a, cp)
    BEGIN
      IF (count8a = '1') THEN  
          a <= '0';
      ELSE
          a <= '1';
      END IF;
    END PROCESS;

-- process count8b, cp.
    PROCESS (count8b, cp)
    BEGIN
      IF (count8b = '1') THEN  
          b <= '0';
      ELSE
          b <= '1';
      END IF;
    END PROCESS;
END a;

顶层文件

VHDL:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY qilei IS
   PORT (
clk,cr, s  : IN   STD_LOGIC;
dididi,a,b   : OUT   STD_LOGIC;
a_8s,a_gewei_50s,a_shiwei50s,b_8s,b_gewei_50s,b_shiwei50s  :OUT   STD_LOGIC_VECTOR (3 DOWNTO 0));
END qilei;

ARCHITECTURE behaveral OF qilei IS

   COMPONENT cnt50s IS
    PORT (
        clk  : IN    STD_LOGIC;
        cir  : IN    STD_LOGIC; 
        en   : IN    STD_LOGIC;
        co   : OUT   STD_LOGIC;
        sunit   : OUT   STD_LOGIC_VECTOR (3 DOWNTO 0);
        stent   : OUT   STD_LOGIC_VECTOR (3 DOWNTO 0)
      );
   END COMPONENT;
		
   COMPONENT cnt8s IS
    PORT (
        clk  : IN    STD_LOGIC;
        cir