BRAM 仿真笔记

mem.v

module mem(
       input clk,
       input en,
       input we,
       input [5:0]addr,
       input [16-1:0]din,
       output reg [16-1:0]dout
);
reg[16-1:0]mem[63:0];
always@(posedge clk)
if(en&we)
    mem[addr]<=din;//读入
 
always@(posedge clk)
if(en)//读请求
   dout<=mem[addr];//读出 （延迟一个时钟输出）
   
endmodule

mem_tb.v

module mem_tb(

    );
    
    reg clk;
    reg rst;
    reg en;
    reg we;
    reg [5:0]addr;
    reg [15:0]din;
    wire [15:0]dout;
    
    
    mem bram_1(
       .clk(clk),
       .en(en),
       .we(we),
       .addr(addr),
       .din(din),
       .dout(dout)
    );
    
initial
begin
clk = 0;
#5
en = 1;
we = 1;
addr = 0;
din = 10;

#10
//en = 0;
addr = 0;
end
    

always #10 clk = ~clk;

    
endmodule

综合结果

仿真结果