SystemVerilog for Design(Chapter2)–SystemVerilog LIteral Value and Build-in Data Types
Topic:
- Enhanced literal values
- `define text substitution enhancements
- Time values
- New variable types
- Variable initialization
- Static and automation variables
- Casting
- Constants
1. Enhanced literal value assignments
1.1 SystemVerilog Enhances assignments of a literal value in two ways.
First, a simpler syntax is added, that allows specifying the fill value without having to specify a radix of binary, octal or hexadecimal.
Second, the fill value can be 1.
- '0 fills all bits on the left-hand side with