vivado2018.3 在调试cameralink接口时,synthesis 和implement都过了,但生成bit文件时报如下错误
[DRC UCIO-1] Unconstrained Logical Port: 6 out of 12 logical ports have no user assigned specific
location constraint (LOC). This may cause I/O contention or incompatibility with the board power
or connectivity affecting performance, signal integrity or in extreme cases cause damage to the
device or the components to which it is connected. To correct this violation, specify all pin
locations. This design will fail to generate a bitstream unless all logical ports have a user
specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations
(not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].
NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command
to a .tcl file and add that file as a pre-hook for write_bitstr