【S000】HDLbits部分笔记

目录

Exams/ece241 2014 q3

---

1. Exams/ece241 2014 q3

module top_module (
	input c,
	input d,
	output [3:0] mux_in
);
	
	// After knowing how to split the truth table into four columns,
	// the rest of this question involves implementing logic functions
	// using only multiplexers (no other gates).
	// I will use the conditional operator for each 2-to-1 mux: (s ? a : b)
	assign mux_in[0] = (c ? 1 : (d ? 1 : 0));	// 2 muxes: c|d
	assign mux_in[1] = 0;						// No muxes:  0
	assign mux_in[2] = d ? 0 : 1;				// 1 mux:    ~d
	assign mux_in[3] = c ? (d ? 1 : 0) : 0;		// 2 muxes: c&d
	
endmodule

Dualedge

module top_module(
    input clk,
    input d,
    output q);
    
    reg p, n;
    
    // A positive-edge triggered flip-flop
    always @(posedge clk)
        p <= d ^ n;
        
    // A negative-edge triggered flip-flop
    always @(negedge clk)
        n <= d ^ p;
    
    // Why does this work? 
    // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
    // After negedge clk, n changes to p^n. Thus q = (p^n) = (p^p^n) = d.
    // At each (positive or negative) clock edge, p and n FFs alternately
    // load a value that will cancel out the other and cause the new value of d to remain.
    assign q = p ^ n;
    
    
    // Can't synthesize this.
    /*always @(posedge clk, negedge clk) begin
        q <= d;
    end*/
    
    
endmodule

module top_module(
    input clk,
    input reset,
    output reg [4:0] q);
    
    reg [4:0] q_next;        // q_next is not a register

    // Convenience: Create a combinational block of logic that computes
    // what the next value should be. For shorter code, I first shift
    // all of the values and then override the two bit positions that have taps.
    // A logic synthesizer creates a circuit that behaves as if the code were
    // executed sequentially, so later assignments override earlier ones.
    // Combinational always block: Use blocking assignments.
    always @(*) begin
        q_next = q[4:1];    // Shift all the bits. This is incorrect for q_next[4] and q_next[2]
        q_next[4] = q[0];    // Give q_next[4] and q_next[2] their correct assignments
        q_next[2] = q[3] ^ q[0];
    end
    
    
    // This is just a set of DFFs. I chose to compute the connections between the
    // DFFs above in its own combinational always block, but you can combine them if you wish.
    // You'll get the same circuit either way.
    // Edge-triggered always block: Use non-blocking assignments.
    always @(posedge clk) begin
        if (reset)
            q <= 5'h1;
        else
            q <= q_next;
    end
    
endmodule