【S022】`ifdef 、 define 、 include 、 generate if 、repeat的使用

目录

 编译小技巧

`ifdef使用格式和优先级

仿真TB

仿真结果

generate if

repeat

---

 编译小技巧

编译do文件加入下面这参数相当于`define SIM_OPEN_NO_EXIST 1 

+define+SIM_OPEN_NO_EXIST

`ifdef使用格式和优先级

下面测试次语句的执行顺序。

结论：代码执行有优先级，只要前面有满足条件的判断，后面的判断不执行（即使后面的条件也满足）。

            `ifdef  SIM_OPEN
                sum = `A +8'd2;
            `elsif SIM_CASE1
                sum = `A +8'd3;
            `elsif SIM_CASE2
                sum = `A +8'd4;
            `else
                sum = `A +8'd5;
            `endif

仿真TB

`timescale 1ns/100ps
`define SIM_OPEN  1 //无等号无分号
`define SIM_CASE1 1  
`define SIM_CASE2 1  
`define A 1 
module tb (  );
    reg [7:0] sum  =8'b0;
    initial  
        begin
            `ifdef  SIM_OPEN
                sum = `A +8'd2;
            `elsif SIM_CASE1
                sum = `A +8'd3;
            `elsif SIM_CASE2
                sum = `A +8'd4;
            `else
                sum = `A +8'd5;
            `endif
            #1;
            $display("sum = %d",sum);// sum = 3

            `ifdef  SIM_OPEN_NO_EXIST
                sum = `A +8'd2;
            `elsif SIM_CASE1
                sum = `A +8'd3;
            `elsif SIM_CASE2
                sum = `A +8'd4;
            `else
                sum = `A +8'd5;
            `endif
            #1;
            $display("sum = %d",sum);// sum = 4
            
            `ifdef  SIM_OPEN_NO_EXIST
                sum = `A +8'd2;
            `elsif SIM_CASE1_NO_EXIST
                sum = `A +8'd3;
            `elsif SIM_CASE2
                sum = `A +8'd4;
            `else
                sum = `A +8'd5;
            `endif
            #1;
            $display("sum = %d",sum);// sum = 5
            
            `ifdef  SIM_OPEN_NO_EXIST
                sum = `A +8'd2;
            `elsif SIM_CASE1_NO_EXIST
                sum = `A +8'd3;
            `elsif SIM_CASE2_NO_EXIST
                sum = `A +8'd4;
            `else
                sum = `A +8'd5;
            `endif
            #1;
            $display("sum = %d",sum);// sum = 6
            //同一路径下
            `include "display.v" //`include diaplay.v print 
        end

endmodule

仿真结果

generate if

module	generate_if(
	input					 t0					,
	input					 t1					,
	input					 t2					,
	output 			        	 d			
);
localparam    S = 6;	            //定义模块所需参数,用于判断产生电路
generate 
	if(S < 7)		
		assign d = t0 | t1 | t2;
	else
		assign d = t0 & t1 & t2;
endgenerate
endmodule

repeat

repeat(循环次数表达式) begin
    语句块;
end

end