generate if verilog 基本用法

generate_if则是根据模块的参数（必须是常量）作为条件判断，来产生满足条件的电路。相当于判断语句。

原语：

 generate
      if (<condition>) begin: <label_1>
         <code>;
      end else if (<condition>) begin: <label_2>
         <code>;
      end else begin: <label_3>
         <code>;
      end
   endgenerate

使用：

module sync_bits #(

  // Number of bits to synchronize
  parameter NUM_OF_BITS = 1,
  // Whether input and output clocks are asynchronous, if 0 the synchronizer will
  // be bypassed and the output signal equals the input signal.
  parameter ASYNC_CLK = 1)(

  input [NUM_OF_BITS-1:0] in_bits,
  input out_resetn,
  input out_clk,
  output [NUM_OF_BITS-1:0] out_bits);

generate 
 if (ASYNC_CLK == 1) begin
     reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
     reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;

     always @(posedge out_clk)
        begin
          if (out_resetn == 1'b0) begin
              cdc_sync_stage1 <= 'b0;
              cdc_sync_stage2 <= 'b0;
           end
         else begin
              cdc_sync_stage1 <= in_bits;
              cdc_sync_stage2 <= cdc_sync_stage1;
          end
     end
     assign out_bits = cdc_sync_stage2;
  end 
else begin
   assign out_bits = in_bits;
   end 
endgenerate

endmodule