定义
FDRE:D Flip-Flop with Clock Enable and Synchronous Reset
FDCE:D Flip-Flop with Clock Enable and AsynchronousReset
FDSE:D Flip-Flop with Clock Enable and Synchronous Set
FDPE:D Flip-Flop with Clock Enable and Asynchronous PresetFD:D Flip-Flop
E :Clock Enable
R :Synchronous Reset
C :Asynchronous Clear
S :Synchronous Set
P :Asynchronous Preset
编译验证
异步复位FDCE
always @(posedge clk or posedge rst) begin
if(rst)
o_data <= #1 1'b0;
else
o_data <= #1 i_data;
end
异步置位FDPE
always @(posedge clk or posedge rst) begin
if(rst)
o_data <= #1 1'b1;
else
o_data <= #1 i_data;
end
同步复位FDRE
always @(posedge clk ) begin
if(rst)
o_data <= #1 1'b0;
else
o_data <= #1 i_data;
end
同步置位FDRE
always @(posedge clk ) begin
if(rst)
o_data <= #1 1'b1;
else
o_data <= #1 i_data;
end
参考