【无标题】ram的verilog建模

RAM建模

ram可以分为两类，分别为Distributed Ram和Block Ram，通过attribute syn_ramstyle可以用于指定ram是否该map到Block Ram或者Distributed Ram或者纯logic的方式.
Decorated object: module, ram instance
Attribute subtype: string
Attribute values: block_ram, select_ram, registers, no_rw_check
Verilog syntax: object/synthesis syn_ramstyle = “block_ram”/;

RAM数据初始化

对于Ram的数据进行初始化赋值，目前ADS综合工具只支持以下两种形式：

穷举初始化

reg [7 : 0] mem [31 : 0] 
initial begin 
    mem[0] = 8'b01111110; 
    mem[1] = 8'b10000011; 
      …… 
    mem[30] = 8'b01110100; 
    mem[31] = 8'b11100101; 
    end 
### $readmemb and $readmemh 文件初始化
reg [3 : 0] mem [0 : 7]; 
initial $readmemb("mem.data", mem); 
// Example of content "mem.data" file 
      1011      // addr=0 
      1000      // addr=1 
      …… 
      1001      // addr=7 
## Distributed Ram 建模
### SINGLE-PORT //do在addr当拍出





always @(posedge clk) 
begin 
      if (en) 
             begin 
             if (we) 
                RAM[addr] <= di; 
             end 
end 
assign do = RAM[addr]; 

###  DUAL_PORT 
always @(posedge clk) 
begin 
             if (en) 
             begin 
                    if (we) 
                           RAM[write_addr] <= di; 
             end 
end 
assign do = RAM[read_addr] 
##  Block Ram 
###  SINGLE_PORT 依据写入时do的不同表现有3种模式。
        1. NORMAL WRITE     ：写入数据的时候，do保持不变。
        2. READ BEFORE WRITE：写入数据的时候，do在wr_en的下一拍，呈现写入之前的数据mem(ADDR0)。
        2. TRANSPARENT WRITE：写入数据的时候，do在wr_en的下一拍，呈现写入当前的数据D0。
//                                        __________     
//  wr_en:                            ___|          |____________
//  addr :                               | ADDR0    | 
//  wr_data :                            | D0       |
//  (NORMAL WRITE     )rd_data :           xx                   | 
//  (READ BEFORE WRITE)rd_data :           xx       | mem(ADDR0)| 
//  (TRANSPARENT WRITE)rd_data :           xx       | D0        | 
#### NORMAL WRITE 
always @(posedge clk) 
begin 
      if (en) 
      begin 
           if (we) 
                    RAM[addr] <= di; 
           else 
                    do <= RAM[addr]; 
      end 
end 
#### READ BEFORE WRITE
always @(posedge clk) 
begin 
      if (en) 
      begin 
             if (we) 
                    RAM[addr] <= di; 
           do <= RAM[addr]; 
      end 
end 
#### TRANSPARENT WRITE0
always @(posedge clk) 
begin 
      if (en) 
      begin 
            if (we) 
            begin 
                    RAM[addr] <= di; 
                    do <= di; 
            end 
           else 
                    do <= RAM[addr]; 
      end 
end 
#### TRANSPARENT WRITE1
always @(posedge clk) 
begin 
      if (en) 
      begin 
           if (we) 
                    RAM[addr] <= di; 
           read_addr <= addr; 
      end 
end 
assign do = RAM[read_addr]; 
###      SIMPLE-DUAL-PORT 
SYNC READ BEFORE WRITE(假定读写时钟相同)
always @(posedge clk) 
begin 
      if (en) 
      begin 
             if (we) 
                    RAM[addra] <= di; 
             dob <= RAM[addrb]; 
      end 
end