CNN模型复现11 ShuffleNetV2

ShuffleNetV2优点：
1、卷积层的输入和输出特征通道数相等时MAC最小，此时模型速度最快。

2、过量使用组卷积会增加MAC。

3、网络碎片化会降低并行度。

4、不能忽略元素级操作，比如ReLU和Add，虽然它们的FLOPs较小，但是却需要较大的MAC。

1. shuffle_unit结构

# strides = 1
input
↓
channel split
↓
P1->conv(1*1)BNRelu->DwConv(3*3)BN->conv(1*1)->p2
↓
concatenate([p1,p2])
↓
channel shuffle


# strides = 2
input->conv(1*1)BNRelu->DwConv(3*3,s=2)BN->conv(1*1)BNRelu->p1
input->DwConv(3*3,s=2)BN->conv(1*1)BNRelu->p2
↓
concatenate([p1,p2])
↓
channel shuffle

2. shuffle_unit代码

'''ShuffleNetV2
# 1.Imports
# 2.Block
    # 2.1 channel_split
    # 2.2 channel_shuffle
    # 2.3 shuffle_unit
    # 2.4 block
# 3.ShuffleNetV2
input[224,224,3]
|
Conv1(24,3,2)+MaxPool(3,2)
|
Stage2(116,s=2,(s=1)*3)
|
Stage3(232,s=2,(s=1)*7)
|
Stage4(464,s=2,(s=1)*3)
|
Conv1(1024,1,1)
|
GlobalPool(7)
|
FC

'''
# 1.Imports
from keras.layers import Input,Lambda,Conv2D,MaxPool2D,Activation,Add,Concatenate,GlobalAveragePooling2D,MaxPooling2D,BatchNormalization,DepthwiseConv2D
import keras.backend as K
from keras.models import Model
import numpy as np

##  2.Block
### 2.1 channel_split
def channel_split(x):
    in_channels = x.shape.as_list()[-1]
    ip = in_channels//2
    c_hat = Lambda(lambda z: z[:,:,:,:ip])(x)
    c = Lambda(lambda z: z[:,:,:,ip:])(x)
    return c_hat,c
### 2.2 channel_shuffle
def channel_shuffle(x):
    h,w,c = x.shape.as_list()[1:]
    channels_per_split = c // 2
    x = K.reshape(x,[-1,h,w,2,channels_per_split])
    x = K.permute_dimensions(x,(0,1,2,4,3))
    x = K.reshape(x,(-1,h,w,c))
    return x

# 2.3 shuffle_unit
def shuffle_unit(inputs, out_channels, bottleneck_ratio, strides=2, stage=1, block=1):
    bn_axis = -1
    bottleneck_channels = int(out_channels * bottleneck_ratio/2)
    if strides < 2:
        c_hat, c = channel_split(inputs, '{}/spl'.format(prefix))
        inputs = c

    x = Conv2D(bottleneck_channels, kernel_size=(1,1), strides=1, padding='same')(inputs)
    x = BatchNormalization(axis=bn_axis)(x)
    x = Activation('relu')(x)

    x = DepthwiseConv2D(kernel_size=3,strides=strides,padding='same')(x)
    x = BatchNormalization(axis=bn_axis)(x)

    x = Conv2D(bottleneck_channels, kernel_size=1, strides=1, padding='same')(inputs)
    x = BatchNormalization(axis=bn_axis)(x)
    x = Activation('relu')(x)

    if strides<2:
        ret = Concatenate(axis=bn_axis)([x,c_hat])
    else:
        s2 = DepthwiseConv2D(kernel_size=3,strides=strides,padding='same')(x)
        s2 = BatchNormalization(axis=bn_axis)(x)

        s2 = Conv2D(bottleneck_channels, kernel_size=1, strides=1, padding='same')(inputs)
        s2 = BatchNormalization(axis=bn_axis)(x)
        s2 = Activation('relu')(x)
        ret = Concatenate(axis=bn_axis)([x,s2])

    return ret


# 2.4 block
def block(x, channel_map, bottleneck_ratio, repeat=1, stage=1):
    x = shuffle_unit(x, out_channels=channel_map[stage-1],
                     strides=2,bottleneck_ratio=bottleneck_ratio,stage=stage,block=1)

    for i in range(1, repeat+1):
        x = shuffle_unit(x, out_channels=channel_map[stage-1],strides=1,
                         bottleneck_ratio=bottleneck_ratio,stage=stage, block=(1+i))

    return x

# 3.ShuffleNetV2
import numpy as np
from keras.utils import plot_model
from keras.layers import Input, Conv2D, MaxPool2D
from keras.layers import Activation, Add, Concatenate, Conv2D
from keras.layers import GlobalAveragePooling2D, Dense
from keras.layers import MaxPool2D,AveragePooling2D, BatchNormalization, Lambda, DepthwiseConv2D
from keras.models import Model
import keras.backend as K

import numpy as np


def channel_split(x, name=''):
    # 输入进来的通道数
    in_channles = x.shape.as_list()[-1]
    ip = in_channles // 2
    # 对通道数进行分割
    c_hat = Lambda(lambda z: z[:, :, :, 0:ip], name='%s/sp%d_slice' % (name, 0))(x)
    c = Lambda(lambda z: z[:, :, :, ip:], name='%s/sp%d_slice' % (name, 1))(x)
    return c_hat, c

def channel_shuffle(x):
    height, width, channels = x.shape.as_list()[1:]
    channels_per_split = channels // 2
    # 通道交换
    x = K.reshape(x, [-1, height, width, 2, channels_per_split])
    x = K.permute_dimensions(x, (0,1,2,4,3))
    x = K.reshape(x, [-1, height, width, channels])
    return x


def shuffle_unit(inputs, out_channels, bottleneck_ratio, strides=2, stage=1, block=1):
    bn_axis = -1

    prefix = 'stage{}/block{}'.format(stage, block)

    # [116, 232, 464]
    bottleneck_channels = int(out_channels * bottleneck_ratio/2)
    if strides < 2:
        c_hat, c = channel_split(inputs, '{}/spl'.format(prefix))
        inputs = c

    # [116, 232, 464]
    x = Conv2D(bottleneck_channels, kernel_size=(1,1), strides=1, padding='same', name='{}/1x1conv_1'.format(prefix))(inputs)
    x = BatchNormalization(axis=bn_axis, name='{}/bn_1x1conv_1'.format(prefix))(x)
    x = Activation('relu', name='{}/relu_1x1conv_1'.format(prefix))(x)

    # 深度可分离卷积
    x = DepthwiseConv2D(kernel_size=3, strides=strides, padding='same', name='{}/3x3dwconv'.format(prefix))(x)
    x = BatchNormalization(axis=bn_axis, name='{}/bn_3x3dwconv'.format(prefix))(x)

    # [116, 232, 464]
    x = Conv2D(bottleneck_channels, kernel_size=1,strides=1,padding='same', name='{}/1x1conv_2'.format(prefix))(x)
    x = BatchNormalization(axis=bn_axis, name='{}/bn_1x1conv_2'.format(prefix))(x)
    x = Activation('relu', name='{}/relu_1x1conv_2'.format(prefix))(x)

    # 当strides等于2的时候，残差边需要添加卷积
    if strides < 2:
        ret = Concatenate(axis=bn_axis, name='{}/concat_1'.format(prefix))([x, c_hat])
    else:
        s2 = DepthwiseConv2D(kernel_size=3, strides=2, padding='same', name='{}/3x3dwconv_2'.format(prefix))(inputs)
        s2 = BatchNormalization(axis=bn_axis, name='{}/bn_3x3dwconv_2'.format(prefix))(s2)

        s2 = Conv2D(bottleneck_channels, kernel_size=1,strides=1,padding='same', name='{}/1x1_conv_3'.format(prefix))(s2)
        s2 = BatchNormalization(axis=bn_axis, name='{}/bn_1x1conv_3'.format(prefix))(s2)
        s2 = Activation('relu', name='{}/relu_1x1conv_3'.format(prefix))(s2)
        ret = Concatenate(axis=bn_axis, name='{}/concat_2'.format(prefix))([x, s2])

    ret = Lambda(channel_shuffle, name='{}/channel_shuffle'.format(prefix))(ret)

    return ret


def block(x, channel_map, bottleneck_ratio, repeat=1, stage=1):
    x = shuffle_unit(x, out_channels=channel_map[stage-1],
                     strides=2,bottleneck_ratio=bottleneck_ratio,stage=stage,block=1)

    for i in range(1, repeat+1):
        x = shuffle_unit(x, out_channels=channel_map[stage-1],strides=1,
                         bottleneck_ratio=bottleneck_ratio,stage=stage, block=(1+i))

    return x

def ShuffleNetV2(input_tensor=None,
                 pooling='max',
                 input_shape=(224,224,3),
                 num_shuffle_units=[3,7,3],
                 scale_factor=1,
                 bottleneck_ratio=1,
                 classes=1000):
    name = 'ShuffleNetV2_{}_{}_{}'.format(scale_factor, bottleneck_ratio, "".join([str(x) for x in num_shuffle_units]))

    out_dim_stage_two = {0.5:48, 1:116, 1.5:176, 2:244}

    out_channels_in_stage = np.array([1,1,2,4])
    out_channels_in_stage *= out_dim_stage_two[scale_factor]  #  calculate output channels for each stage
    out_channels_in_stage[0] = 24  # first stage has always 24 output channels
    out_channels_in_stage = out_channels_in_stage.astype(int)

    img_input = Input(shape=input_shape)

    x = Conv2D(filters=out_channels_in_stage[0], kernel_size=(3, 3), padding='same', use_bias=False, strides=(2, 2),
               activation='relu', name='conv1')(img_input)
    x = MaxPool2D(pool_size=(3, 3), strides=(2, 2), padding='same', name='maxpool1')(x)

    for stage in range(len(num_shuffle_units)):
        repeat = num_shuffle_units[stage]
        x = block(x, out_channels_in_stage,
                  repeat=repeat,
                  bottleneck_ratio=bottleneck_ratio,
                  stage=stage + 2)

    if scale_factor!=2:
        x = Conv2D(1024, kernel_size=1, padding='same', strides=1, name='1x1conv5_out', activation='relu')(x)
    else:
        x = Conv2D(2048, kernel_size=1, padding='same', strides=1, name='1x1conv5_out', activation='relu')(x)
    x = GlobalAveragePooling2D(name='global_avg_pool')(x)

    x = Dense(classes, name='fc')(x)
    x = Activation('softmax', name='softmax')(x)

    inputs = img_input

    model = Model(inputs, x, name=name)

    return model

if __name__ == '__main__':
    import os
    os.environ['CUDA_VISIBLE_DEVICES'] = ''
    model = ShuffleNetV2(input_shape=(224, 224, 3),scale_factor=1)
    model.summary()
'''
__________________________________________________________________________________________________
Layer (type)                    Output Shape         Param #     Connected to                     
==================================================================================================
input_1 (InputLayer)            (None, 224, 224, 3)  0                                            
__________________________________________________________________________________________________
conv1 (Conv2D)                  (None, 112, 112, 24) 648         input_1[0][0]                    
__________________________________________________________________________________________________
maxpool1 (MaxPooling2D)         (None, 56, 56, 24)   0           conv1[0][0]                      
__________________________________________________________________________________________________
stage2/block1/1x1conv_1 (Conv2D (None, 56, 56, 58)   1450        maxpool1[0][0]                   
__________________________________________________________________________________________________
stage2/block1/bn_1x1conv_1 (Bat (None, 56, 56, 58)   232         stage2/block1/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage2/block1/relu_1x1conv_1 (A (None, 56, 56, 58)   0           stage2/block1/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage2/block1/3x3dwconv (Depthw (None, 28, 28, 58)   580         stage2/block1/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage2/block1/3x3dwconv_2 (Dept (None, 28, 28, 24)   240         maxpool1[0][0]                   
__________________________________________________________________________________________________
stage2/block1/bn_3x3dwconv (Bat (None, 28, 28, 58)   232         stage2/block1/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage2/block1/bn_3x3dwconv_2 (B (None, 28, 28, 24)   96          stage2/block1/3x3dwconv_2[0][0]  
__________________________________________________________________________________________________
stage2/block1/1x1conv_2 (Conv2D (None, 28, 28, 58)   3422        stage2/block1/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage2/block1/1x1_conv_3 (Conv2 (None, 28, 28, 58)   1450        stage2/block1/bn_3x3dwconv_2[0][0
__________________________________________________________________________________________________
stage2/block1/bn_1x1conv_2 (Bat (None, 28, 28, 58)   232         stage2/block1/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage2/block1/bn_1x1conv_3 (Bat (None, 28, 28, 58)   232         stage2/block1/1x1_conv_3[0][0]   
__________________________________________________________________________________________________
stage2/block1/relu_1x1conv_2 (A (None, 28, 28, 58)   0           stage2/block1/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage2/block1/relu_1x1conv_3 (A (None, 28, 28, 58)   0           stage2/block1/bn_1x1conv_3[0][0] 
__________________________________________________________________________________________________
stage2/block1/concat_2 (Concate (None, 28, 28, 116)  0           stage2/block1/relu_1x1conv_2[0][0
                                                                 stage2/block1/relu_1x1conv_3[0][0
__________________________________________________________________________________________________
stage2/block1/channel_shuffle ( (None, 28, 28, 116)  0           stage2/block1/concat_2[0][0]     
__________________________________________________________________________________________________
stage2/block2/spl/sp1_slice (La (None, 28, 28, 58)   0           stage2/block1/channel_shuffle[0][
__________________________________________________________________________________________________
stage2/block2/1x1conv_1 (Conv2D (None, 28, 28, 58)   3422        stage2/block2/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage2/block2/bn_1x1conv_1 (Bat (None, 28, 28, 58)   232         stage2/block2/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage2/block2/relu_1x1conv_1 (A (None, 28, 28, 58)   0           stage2/block2/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage2/block2/3x3dwconv (Depthw (None, 28, 28, 58)   580         stage2/block2/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage2/block2/bn_3x3dwconv (Bat (None, 28, 28, 58)   232         stage2/block2/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage2/block2/1x1conv_2 (Conv2D (None, 28, 28, 58)   3422        stage2/block2/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage2/block2/bn_1x1conv_2 (Bat (None, 28, 28, 58)   232         stage2/block2/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage2/block2/relu_1x1conv_2 (A (None, 28, 28, 58)   0           stage2/block2/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage2/block2/spl/sp0_slice (La (None, 28, 28, 58)   0           stage2/block1/channel_shuffle[0][
__________________________________________________________________________________________________
stage2/block2/concat_1 (Concate (None, 28, 28, 116)  0           stage2/block2/relu_1x1conv_2[0][0
                                                                 stage2/block2/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage2/block2/channel_shuffle ( (None, 28, 28, 116)  0           stage2/block2/concat_1[0][0]     
__________________________________________________________________________________________________
stage2/block3/spl/sp1_slice (La (None, 28, 28, 58)   0           stage2/block2/channel_shuffle[0][
__________________________________________________________________________________________________
stage2/block3/1x1conv_1 (Conv2D (None, 28, 28, 58)   3422        stage2/block3/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage2/block3/bn_1x1conv_1 (Bat (None, 28, 28, 58)   232         stage2/block3/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage2/block3/relu_1x1conv_1 (A (None, 28, 28, 58)   0           stage2/block3/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage2/block3/3x3dwconv (Depthw (None, 28, 28, 58)   580         stage2/block3/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage2/block3/bn_3x3dwconv (Bat (None, 28, 28, 58)   232         stage2/block3/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage2/block3/1x1conv_2 (Conv2D (None, 28, 28, 58)   3422        stage2/block3/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage2/block3/bn_1x1conv_2 (Bat (None, 28, 28, 58)   232         stage2/block3/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage2/block3/relu_1x1conv_2 (A (None, 28, 28, 58)   0           stage2/block3/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage2/block3/spl/sp0_slice (La (None, 28, 28, 58)   0           stage2/block2/channel_shuffle[0][
__________________________________________________________________________________________________
stage2/block3/concat_1 (Concate (None, 28, 28, 116)  0           stage2/block3/relu_1x1conv_2[0][0
                                                                 stage2/block3/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage2/block3/channel_shuffle ( (None, 28, 28, 116)  0           stage2/block3/concat_1[0][0]     
__________________________________________________________________________________________________
stage2/block4/spl/sp1_slice (La (None, 28, 28, 58)   0           stage2/block3/channel_shuffle[0][
__________________________________________________________________________________________________
stage2/block4/1x1conv_1 (Conv2D (None, 28, 28, 58)   3422        stage2/block4/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage2/block4/bn_1x1conv_1 (Bat (None, 28, 28, 58)   232         stage2/block4/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage2/block4/relu_1x1conv_1 (A (None, 28, 28, 58)   0           stage2/block4/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage2/block4/3x3dwconv (Depthw (None, 28, 28, 58)   580         stage2/block4/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage2/block4/bn_3x3dwconv (Bat (None, 28, 28, 58)   232         stage2/block4/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage2/block4/1x1conv_2 (Conv2D (None, 28, 28, 58)   3422        stage2/block4/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage2/block4/bn_1x1conv_2 (Bat (None, 28, 28, 58)   232         stage2/block4/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage2/block4/relu_1x1conv_2 (A (None, 28, 28, 58)   0           stage2/block4/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage2/block4/spl/sp0_slice (La (None, 28, 28, 58)   0           stage2/block3/channel_shuffle[0][
__________________________________________________________________________________________________
stage2/block4/concat_1 (Concate (None, 28, 28, 116)  0           stage2/block4/relu_1x1conv_2[0][0
                                                                 stage2/block4/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage2/block4/channel_shuffle ( (None, 28, 28, 116)  0           stage2/block4/concat_1[0][0]     
__________________________________________________________________________________________________
stage3/block1/1x1conv_1 (Conv2D (None, 28, 28, 116)  13572       stage2/block4/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block1/bn_1x1conv_1 (Bat (None, 28, 28, 116)  464         stage3/block1/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage3/block1/relu_1x1conv_1 (A (None, 28, 28, 116)  0           stage3/block1/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage3/block1/3x3dwconv (Depthw (None, 14, 14, 116)  1160        stage3/block1/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage3/block1/3x3dwconv_2 (Dept (None, 14, 14, 116)  1160        stage2/block4/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block1/bn_3x3dwconv (Bat (None, 14, 14, 116)  464         stage3/block1/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage3/block1/bn_3x3dwconv_2 (B (None, 14, 14, 116)  464         stage3/block1/3x3dwconv_2[0][0]  
__________________________________________________________________________________________________
stage3/block1/1x1conv_2 (Conv2D (None, 14, 14, 116)  13572       stage3/block1/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage3/block1/1x1_conv_3 (Conv2 (None, 14, 14, 116)  13572       stage3/block1/bn_3x3dwconv_2[0][0
__________________________________________________________________________________________________
stage3/block1/bn_1x1conv_2 (Bat (None, 14, 14, 116)  464         stage3/block1/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage3/block1/bn_1x1conv_3 (Bat (None, 14, 14, 116)  464         stage3/block1/1x1_conv_3[0][0]   
__________________________________________________________________________________________________
stage3/block1/relu_1x1conv_2 (A (None, 14, 14, 116)  0           stage3/block1/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage3/block1/relu_1x1conv_3 (A (None, 14, 14, 116)  0           stage3/block1/bn_1x1conv_3[0][0] 
__________________________________________________________________________________________________
stage3/block1/concat_2 (Concate (None, 14, 14, 232)  0           stage3/block1/relu_1x1conv_2[0][0
                                                                 stage3/block1/relu_1x1conv_3[0][0
__________________________________________________________________________________________________
stage3/block1/channel_shuffle ( (None, 14, 14, 232)  0           stage3/block1/concat_2[0][0]     
__________________________________________________________________________________________________
stage3/block2/spl/sp1_slice (La (None, 14, 14, 116)  0           stage3/block1/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block2/1x1conv_1 (Conv2D (None, 14, 14, 116)  13572       stage3/block2/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage3/block2/bn_1x1conv_1 (Bat (None, 14, 14, 116)  464         stage3/block2/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage3/block2/relu_1x1conv_1 (A (None, 14, 14, 116)  0           stage3/block2/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage3/block2/3x3dwconv (Depthw (None, 14, 14, 116)  1160        stage3/block2/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage3/block2/bn_3x3dwconv (Bat (None, 14, 14, 116)  464         stage3/block2/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage3/block2/1x1conv_2 (Conv2D (None, 14, 14, 116)  13572       stage3/block2/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage3/block2/bn_1x1conv_2 (Bat (None, 14, 14, 116)  464         stage3/block2/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage3/block2/relu_1x1conv_2 (A (None, 14, 14, 116)  0           stage3/block2/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage3/block2/spl/sp0_slice (La (None, 14, 14, 116)  0           stage3/block1/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block2/concat_1 (Concate (None, 14, 14, 232)  0           stage3/block2/relu_1x1conv_2[0][0
                                                                 stage3/block2/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage3/block2/channel_shuffle ( (None, 14, 14, 232)  0           stage3/block2/concat_1[0][0]     
__________________________________________________________________________________________________
stage3/block3/spl/sp1_slice (La (None, 14, 14, 116)  0           stage3/block2/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block3/1x1conv_1 (Conv2D (None, 14, 14, 116)  13572       stage3/block3/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage3/block3/bn_1x1conv_1 (Bat (None, 14, 14, 116)  464         stage3/block3/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage3/block3/relu_1x1conv_1 (A (None, 14, 14, 116)  0           stage3/block3/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage3/block3/3x3dwconv (Depthw (None, 14, 14, 116)  1160        stage3/block3/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage3/block3/bn_3x3dwconv (Bat (None, 14, 14, 116)  464         stage3/block3/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage3/block3/1x1conv_2 (Conv2D (None, 14, 14, 116)  13572       stage3/block3/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage3/block3/bn_1x1conv_2 (Bat (None, 14, 14, 116)  464         stage3/block3/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage3/block3/relu_1x1conv_2 (A (None, 14, 14, 116)  0           stage3/block3/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage3/block3/spl/sp0_slice (La (None, 14, 14, 116)  0           stage3/block2/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block3/concat_1 (Concate (None, 14, 14, 232)  0           stage3/block3/relu_1x1conv_2[0][0
                                                                 stage3/block3/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage3/block3/channel_shuffle ( (None, 14, 14, 232)  0           stage3/block3/concat_1[0][0]     
__________________________________________________________________________________________________
stage3/block4/spl/sp1_slice (La (None, 14, 14, 116)  0           stage3/block3/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block4/1x1conv_1 (Conv2D (None, 14, 14, 116)  13572       stage3/block4/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage3/block4/bn_1x1conv_1 (Bat (None, 14, 14, 116)  464         stage3/block4/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage3/block4/relu_1x1conv_1 (A (None, 14, 14, 116)  0           stage3/block4/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage3/block4/3x3dwconv (Depthw (None, 14, 14, 116)  1160        stage3/block4/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage3/block4/bn_3x3dwconv (Bat (None, 14, 14, 116)  464         stage3/block4/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage3/block4/1x1conv_2 (Conv2D (None, 14, 14, 116)  13572       stage3/block4/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage3/block4/bn_1x1conv_2 (Bat (None, 14, 14, 116)  464         stage3/block4/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage3/block4/relu_1x1conv_2 (A (None, 14, 14, 116)  0           stage3/block4/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage3/block4/spl/sp0_slice (La (None, 14, 14, 116)  0           stage3/block3/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block4/concat_1 (Concate (None, 14, 14, 232)  0           stage3/block4/relu_1x1conv_2[0][0
                                                                 stage3/block4/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage3/block4/channel_shuffle ( (None, 14, 14, 232)  0           stage3/block4/concat_1[0][0]     
__________________________________________________________________________________________________
stage3/block5/spl/sp1_slice (La (None, 14, 14, 116)  0           stage3/block4/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block5/1x1conv_1 (Conv2D (None, 14, 14, 116)  13572       stage3/block5/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage3/block5/bn_1x1conv_1 (Bat (None, 14, 14, 116)  464         stage3/block5/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage3/block5/relu_1x1conv_1 (A (None, 14, 14, 116)  0           stage3/block5/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage3/block5/3x3dwconv (Depthw (None, 14, 14, 116)  1160        stage3/block5/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage3/block5/bn_3x3dwconv (Bat (None, 14, 14, 116)  464         stage3/block5/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage3/block5/1x1conv_2 (Conv2D (None, 14, 14, 116)  13572       stage3/block5/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage3/block5/bn_1x1conv_2 (Bat (None, 14, 14, 116)  464         stage3/block5/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage3/block5/relu_1x1conv_2 (A (None, 14, 14, 116)  0           stage3/block5/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage3/block5/spl/sp0_slice (La (None, 14, 14, 116)  0           stage3/block4/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block5/concat_1 (Concate (None, 14, 14, 232)  0           stage3/block5/relu_1x1conv_2[0][0
                                                                 stage3/block5/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage3/block5/channel_shuffle ( (None, 14, 14, 232)  0           stage3/block5/concat_1[0][0]     
__________________________________________________________________________________________________
stage3/block6/spl/sp1_slice (La (None, 14, 14, 116)  0           stage3/block5/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block6/1x1conv_1 (Conv2D (None, 14, 14, 116)  13572       stage3/block6/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage3/block6/bn_1x1conv_1 (Bat (None, 14, 14, 116)  464         stage3/block6/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage3/block6/relu_1x1conv_1 (A (None, 14, 14, 116)  0           stage3/block6/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage3/block6/3x3dwconv (Depthw (None, 14, 14, 116)  1160        stage3/block6/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage3/block6/bn_3x3dwconv (Bat (None, 14, 14, 116)  464         stage3/block6/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage3/block6/1x1conv_2 (Conv2D (None, 14, 14, 116)  13572       stage3/block6/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage3/block6/bn_1x1conv_2 (Bat (None, 14, 14, 116)  464         stage3/block6/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage3/block6/relu_1x1conv_2 (A (None, 14, 14, 116)  0           stage3/block6/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage3/block6/spl/sp0_slice (La (None, 14, 14, 116)  0           stage3/block5/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block6/concat_1 (Concate (None, 14, 14, 232)  0           stage3/block6/relu_1x1conv_2[0][0
                                                                 stage3/block6/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage3/block6/channel_shuffle ( (None, 14, 14, 232)  0           stage3/block6/concat_1[0][0]     
__________________________________________________________________________________________________
stage3/block7/spl/sp1_slice (La (None, 14, 14, 116)  0           stage3/block6/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block7/1x1conv_1 (Conv2D (None, 14, 14, 116)  13572       stage3/block7/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage3/block7/bn_1x1conv_1 (Bat (None, 14, 14, 116)  464         stage3/block7/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage3/block7/relu_1x1conv_1 (A (None, 14, 14, 116)  0           stage3/block7/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage3/block7/3x3dwconv (Depthw (None, 14, 14, 116)  1160        stage3/block7/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage3/block7/bn_3x3dwconv (Bat (None, 14, 14, 116)  464         stage3/block7/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage3/block7/1x1conv_2 (Conv2D (None, 14, 14, 116)  13572       stage3/block7/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage3/block7/bn_1x1conv_2 (Bat (None, 14, 14, 116)  464         stage3/block7/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage3/block7/relu_1x1conv_2 (A (None, 14, 14, 116)  0           stage3/block7/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage3/block7/spl/sp0_slice (La (None, 14, 14, 116)  0           stage3/block6/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block7/concat_1 (Concate (None, 14, 14, 232)  0           stage3/block7/relu_1x1conv_2[0][0
                                                                 stage3/block7/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage3/block7/channel_shuffle ( (None, 14, 14, 232)  0           stage3/block7/concat_1[0][0]     
__________________________________________________________________________________________________
stage3/block8/spl/sp1_slice (La (None, 14, 14, 116)  0           stage3/block7/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block8/1x1conv_1 (Conv2D (None, 14, 14, 116)  13572       stage3/block8/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage3/block8/bn_1x1conv_1 (Bat (None, 14, 14, 116)  464         stage3/block8/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage3/block8/relu_1x1conv_1 (A (None, 14, 14, 116)  0           stage3/block8/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage3/block8/3x3dwconv (Depthw (None, 14, 14, 116)  1160        stage3/block8/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage3/block8/bn_3x3dwconv (Bat (None, 14, 14, 116)  464         stage3/block8/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage3/block8/1x1conv_2 (Conv2D (None, 14, 14, 116)  13572       stage3/block8/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage3/block8/bn_1x1conv_2 (Bat (None, 14, 14, 116)  464         stage3/block8/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage3/block8/relu_1x1conv_2 (A (None, 14, 14, 116)  0           stage3/block8/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage3/block8/spl/sp0_slice (La (None, 14, 14, 116)  0           stage3/block7/channel_shuffle[0][
__________________________________________________________________________________________________
stage3/block8/concat_1 (Concate (None, 14, 14, 232)  0           stage3/block8/relu_1x1conv_2[0][0
                                                                 stage3/block8/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage3/block8/channel_shuffle ( (None, 14, 14, 232)  0           stage3/block8/concat_1[0][0]     
__________________________________________________________________________________________________
stage4/block1/1x1conv_1 (Conv2D (None, 14, 14, 232)  54056       stage3/block8/channel_shuffle[0][
__________________________________________________________________________________________________
stage4/block1/bn_1x1conv_1 (Bat (None, 14, 14, 232)  928         stage4/block1/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage4/block1/relu_1x1conv_1 (A (None, 14, 14, 232)  0           stage4/block1/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage4/block1/3x3dwconv (Depthw (None, 7, 7, 232)    2320        stage4/block1/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage4/block1/3x3dwconv_2 (Dept (None, 7, 7, 232)    2320        stage3/block8/channel_shuffle[0][
__________________________________________________________________________________________________
stage4/block1/bn_3x3dwconv (Bat (None, 7, 7, 232)    928         stage4/block1/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage4/block1/bn_3x3dwconv_2 (B (None, 7, 7, 232)    928         stage4/block1/3x3dwconv_2[0][0]  
__________________________________________________________________________________________________
stage4/block1/1x1conv_2 (Conv2D (None, 7, 7, 232)    54056       stage4/block1/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage4/block1/1x1_conv_3 (Conv2 (None, 7, 7, 232)    54056       stage4/block1/bn_3x3dwconv_2[0][0
__________________________________________________________________________________________________
stage4/block1/bn_1x1conv_2 (Bat (None, 7, 7, 232)    928         stage4/block1/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage4/block1/bn_1x1conv_3 (Bat (None, 7, 7, 232)    928         stage4/block1/1x1_conv_3[0][0]   
__________________________________________________________________________________________________
stage4/block1/relu_1x1conv_2 (A (None, 7, 7, 232)    0           stage4/block1/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage4/block1/relu_1x1conv_3 (A (None, 7, 7, 232)    0           stage4/block1/bn_1x1conv_3[0][0] 
__________________________________________________________________________________________________
stage4/block1/concat_2 (Concate (None, 7, 7, 464)    0           stage4/block1/relu_1x1conv_2[0][0
                                                                 stage4/block1/relu_1x1conv_3[0][0
__________________________________________________________________________________________________
stage4/block1/channel_shuffle ( (None, 7, 7, 464)    0           stage4/block1/concat_2[0][0]     
__________________________________________________________________________________________________
stage4/block2/spl/sp1_slice (La (None, 7, 7, 232)    0           stage4/block1/channel_shuffle[0][
__________________________________________________________________________________________________
stage4/block2/1x1conv_1 (Conv2D (None, 7, 7, 232)    54056       stage4/block2/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage4/block2/bn_1x1conv_1 (Bat (None, 7, 7, 232)    928         stage4/block2/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage4/block2/relu_1x1conv_1 (A (None, 7, 7, 232)    0           stage4/block2/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage4/block2/3x3dwconv (Depthw (None, 7, 7, 232)    2320        stage4/block2/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage4/block2/bn_3x3dwconv (Bat (None, 7, 7, 232)    928         stage4/block2/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage4/block2/1x1conv_2 (Conv2D (None, 7, 7, 232)    54056       stage4/block2/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage4/block2/bn_1x1conv_2 (Bat (None, 7, 7, 232)    928         stage4/block2/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage4/block2/relu_1x1conv_2 (A (None, 7, 7, 232)    0           stage4/block2/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage4/block2/spl/sp0_slice (La (None, 7, 7, 232)    0           stage4/block1/channel_shuffle[0][
__________________________________________________________________________________________________
stage4/block2/concat_1 (Concate (None, 7, 7, 464)    0           stage4/block2/relu_1x1conv_2[0][0
                                                                 stage4/block2/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage4/block2/channel_shuffle ( (None, 7, 7, 464)    0           stage4/block2/concat_1[0][0]     
__________________________________________________________________________________________________
stage4/block3/spl/sp1_slice (La (None, 7, 7, 232)    0           stage4/block2/channel_shuffle[0][
__________________________________________________________________________________________________
stage4/block3/1x1conv_1 (Conv2D (None, 7, 7, 232)    54056       stage4/block3/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage4/block3/bn_1x1conv_1 (Bat (None, 7, 7, 232)    928         stage4/block3/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage4/block3/relu_1x1conv_1 (A (None, 7, 7, 232)    0           stage4/block3/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage4/block3/3x3dwconv (Depthw (None, 7, 7, 232)    2320        stage4/block3/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage4/block3/bn_3x3dwconv (Bat (None, 7, 7, 232)    928         stage4/block3/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage4/block3/1x1conv_2 (Conv2D (None, 7, 7, 232)    54056       stage4/block3/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage4/block3/bn_1x1conv_2 (Bat (None, 7, 7, 232)    928         stage4/block3/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage4/block3/relu_1x1conv_2 (A (None, 7, 7, 232)    0           stage4/block3/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage4/block3/spl/sp0_slice (La (None, 7, 7, 232)    0           stage4/block2/channel_shuffle[0][
__________________________________________________________________________________________________
stage4/block3/concat_1 (Concate (None, 7, 7, 464)    0           stage4/block3/relu_1x1conv_2[0][0
                                                                 stage4/block3/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage4/block3/channel_shuffle ( (None, 7, 7, 464)    0           stage4/block3/concat_1[0][0]     
__________________________________________________________________________________________________
stage4/block4/spl/sp1_slice (La (None, 7, 7, 232)    0           stage4/block3/channel_shuffle[0][
__________________________________________________________________________________________________
stage4/block4/1x1conv_1 (Conv2D (None, 7, 7, 232)    54056       stage4/block4/spl/sp1_slice[0][0]
__________________________________________________________________________________________________
stage4/block4/bn_1x1conv_1 (Bat (None, 7, 7, 232)    928         stage4/block4/1x1conv_1[0][0]    
__________________________________________________________________________________________________
stage4/block4/relu_1x1conv_1 (A (None, 7, 7, 232)    0           stage4/block4/bn_1x1conv_1[0][0] 
__________________________________________________________________________________________________
stage4/block4/3x3dwconv (Depthw (None, 7, 7, 232)    2320        stage4/block4/relu_1x1conv_1[0][0
__________________________________________________________________________________________________
stage4/block4/bn_3x3dwconv (Bat (None, 7, 7, 232)    928         stage4/block4/3x3dwconv[0][0]    
__________________________________________________________________________________________________
stage4/block4/1x1conv_2 (Conv2D (None, 7, 7, 232)    54056       stage4/block4/bn_3x3dwconv[0][0] 
__________________________________________________________________________________________________
stage4/block4/bn_1x1conv_2 (Bat (None, 7, 7, 232)    928         stage4/block4/1x1conv_2[0][0]    
__________________________________________________________________________________________________
stage4/block4/relu_1x1conv_2 (A (None, 7, 7, 232)    0           stage4/block4/bn_1x1conv_2[0][0] 
__________________________________________________________________________________________________
stage4/block4/spl/sp0_slice (La (None, 7, 7, 232)    0           stage4/block3/channel_shuffle[0][
__________________________________________________________________________________________________
stage4/block4/concat_1 (Concate (None, 7, 7, 464)    0           stage4/block4/relu_1x1conv_2[0][0
                                                                 stage4/block4/spl/sp0_slice[0][0]
__________________________________________________________________________________________________
stage4/block4/channel_shuffle ( (None, 7, 7, 464)    0           stage4/block4/concat_1[0][0]     
__________________________________________________________________________________________________
1x1conv5_out (Conv2D)           (None, 7, 7, 1024)   476160      stage4/block4/channel_shuffle[0][
__________________________________________________________________________________________________
global_avg_pool (GlobalAverageP (None, 1024)         0           1x1conv5_out[0][0]               
__________________________________________________________________________________________________
fc (Dense)                      (None, 1000)         1025000     global_avg_pool[0][0]            
__________________________________________________________________________________________________
softmax (Activation)            (None, 1000)         0           fc[0][0]                         
==================================================================================================
Total params: 2,298,658
Trainable params: 2,284,574
Non-trainable params: 14,084
__________________________________________________________________________________________________

Process finished with exit code 0
'''