记录错误:vivado计数器一直X态
错误代码:
always @ (posedge clk )begin
if (reset)begin
clk_div2<=1’b0;
end else begin
clk_div2<= ~clk_div2;
end
end
always @(posedge clk_div2) begin
if(reset ==1)begin
write_addr<=0;
end else begin
write_addr<=write_addr+1;
end
end
错误表现:
write_addr一直是X态,数据流如下(clk即上文的clk_div2)
错误分析:reset先失效,但此时clk的上升沿没有来临,所以write_addr的初始值没有起来。
错误借鉴意义:clkreset 不应该和 datareset 是同一个信号,且clkreset应该先失效,保证clk先准备好!
正确代码:
always @ (posedge clk )begin
clk_div2<= ~clk_div2;
end
always @(posedge clk_div2) begin
if(reset ==1)begin
write_addr<=0;
end else begin
write_addr<=write_addr+1;
end
end
正确的数据流:(clk即上文的clk_div2)