注意程序中Verilog位扩展的写法
{led_num{1’b0}} 相当于把 1’b0复制 led_num 次,数据总长为led_num位。
{led_num{2’b01}} 数据总长为 2*led_num 位
二级文件
`timescale 1 ns / 1 ps
module LED_test (
clk,
rst_n,
led
);
parameter led_num = 4;
input clk, rst_n;
output [led_num - 1:0] led;
reg [led_num - 1:0] led = {led_num{1'b0}};
reg [31:0] time_cnt = 32'b0;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
led <= {led_num{1'b0}};
time_cnt <= 32'd0;
end
else
begin
if(time_cnt >= 32'd0 && time_cnt < 32'd24999999)
begin
time_cnt <= time_cnt + 32'd1;
led <= led;
end
else if(time_cnt == 32'd24999999)
begin
if(led == {led_num{1'b0}})
led <= {{led_num - 1{1'b0}},1'b1};
else if(led == {1'b1,{led_num - 1{1'b0}}})
led <= {{led_num - 1{1'b0}},1'b1};
else
led <= led << 1;
time_cnt <= 32'd0;
end
else
begin
led <= {led_num{1'b0}};
time_cnt <= 32'd0;
end
end
end
endmodule
一级文件
`timescale 1 ns / 1 ps
module LED(
clk,
rst_n,
led
);
parameter led_num = 4;
input clk, rst_n;
output [led_num - 1:0] led;
LED_test #(
.led_num(led_num) //注意参数传递的写法
)
LED_test_inst(
.clk(clk),
.rst_n(rst_n),
.led(led)
);
endmodule