matlab
STR = "55 AA CF 12 71 7B FF 04 71 01 00 00 84 39 C0 70 0F 00 00 00 00 03 00 " + ...
"00 00 00 00 00 03 00 FF FF 02 00 00 00 00 00 00 00 00 00 00 00 00 00 D3 " + ...
"03 FB FF 12 00 00 00 00 00 00 00 00 00 C4 09 00 00 00 00 00 00 C4 09 00 " + ...
"96 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 " + ...
"00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 83 62 8A 62 55 09 E0 " + ...
"FF 10 0B 00 0D 7A 00 00 32 00 00 00 00 00 00 00 00 32 EC FF 13 00 ED FF " + ...
"EC FF 10 00 00 1A 00 00 00 19 00 00 00 00 00 00 00 00 28 00 08 EA 6C 03 " + ...
"00 01 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 " + ...
"00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 AE 10 4C 15 2E";
C = strsplit(STR," ");
LEN = length(C);
for i = 1:LEN
disp("32'd"+i+":begin dout<=8'h"+C(i)+"; end");
end
生成的代码可以复制到Verilog的 case结构中使用