ZYNQ PS例程


/********************MIO示例********************/

#include <stdio.h>
#include <xparameters.h>
#include <xgpiops.h>
#include <sleep.h>


#define GPIO_DEVICE_ID  	XPAR_XGPIOPS_0_DEVICE_ID//GPIO设备号定义

int main()
{
	//1、驱动初始化
	XGpioPs_Config *ConfigPtr;//配置信息块
	XGpioPs        Gpio;      //GPIO实例
	
	ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID);//获取配置信息
	XGpioPs_CfgInitialize(&Gpio, ConfigPtr,ConfigPtr->BaseAddr);//初始化实例

	//2、MIO引脚配置
	unsigned int Output_Pin = 0;//引脚号(0-53)
	
	XGpioPs_SetDirectionPin(&Gpio, Output_Pin, 1);//IO方向配置(输出)
	XGpioPs_SetOutputEnablePin(&Gpio, Output_Pin, 1);//输出使能

	while(1)
	{
		XGpioPs_WritePin(&Gpio, Output_Pin, 0);//写0
		sleep(1);
		XGpioPs_WritePin(&Gpio, Output_Pin, 1);//写1
		sleep(1);
	}

	return 0;
}


/********************EMIO示例********************/

#include <stdio.h>
#include <xparameters.h>
#include <xgpiops.h>
#include <sleep.h>


#define GPIO_DEVICE_ID  	XPA
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是的,有Zynq NVMe例程。以下是一个基本的Zynq NVMe例程,该例程使用Zynq的PCIe接口连接到NVMe设备: ```c #include <stdlib.h> #include <stdio.h> #include <xil_printf.h> #include <xil_io.h> #define NVME_BAR0_ADDR 0x10000000 #define NVME_BAR1_ADDR 0x10100000 #define NVME_CAP 0x00 #define NVME_VS 0x08 #define NVME_INTMS 0x0C #define NVME_INTMC 0x10 #define NVME_CC 0x14 #define NVME_CSTS 0x1C #define NVME_AQA 0x24 #define NVME_ASQ 0x28 #define NVME_ACQ 0x30 void nvme_write_reg(u32 reg_addr, u32 value) { Xil_Out32(NVME_BAR0_ADDR + reg_addr, value); } u32 nvme_read_reg(u32 reg_addr) { return Xil_In32(NVME_BAR0_ADDR + reg_addr); } int main() { // Reset the NVMe controller nvme_write_reg(NVME_CC, 0x00000001); while (nvme_read_reg(NVME_CSTS) & 0x00000001); // Configure the NVMe controller nvme_write_reg(NVME_CAP, 0x00000000); nvme_write_reg(NVME_VS, 0x00010000); nvme_write_reg(NVME_INTMS, 0x00000000); nvme_write_reg(NVME_INTMC, 0xFFFFFFFF); nvme_write_reg(NVME_AQA, 0x00000000); nvme_write_reg(NVME_ASQ, NVME_BAR1_ADDR); nvme_write_reg(NVME_ACQ, NVME_BAR1_ADDR + 0x1000); nvme_write_reg(NVME_CC, 0x00000007); // Wait for the NVMe controller to be ready while ((nvme_read_reg(NVME_CSTS) & 0x00000001) == 0); // Issue a Identify Controller command nvme_write_reg(NVME_ASQ + 0x00, 0x00000006); nvme_write_reg(NVME_ASQ + 0x04, 0x00000000); nvme_write_reg(NVME_ASQ + 0x08, 0x00000000); nvme_write_reg(NVME_ASQ + 0x0C, 0x00000000); nvme_write_reg(NVME_ASQ + 0x10, 0x00000000); nvme_write_reg(NVME_ASQ + 0x14, 0x00000000); nvme_write_reg(NVME_ASQ + 0x18, 0x00000000); nvme_write_reg(NVME_ASQ + 0x1C, 0x00000000); nvme_write_reg(NVME_ASQ + 0x20, 0x00000000); nvme_write_reg(NVME_ASQ + 0x24, 0x00000000); nvme_write_reg(NVME_ASQ + 0x28, 0x00000000); nvme_write_reg(NVME_ASQ + 0x2C, 0x00000000); nvme_write_reg(NVME_ASQ + 0x30, 0x00000000); nvme_write_reg(NVME_ASQ + 0x34, 0x00000000); nvme_write_reg(NVME_ASQ + 0x38, 0x00000000); nvme_write_reg(NVME_ASQ + 0x3C, 0x00000000); nvme_write_reg(NVME_ASQ + 0x40, 0x00000000); nvme_write_reg(NVME_ASQ + 0x44, 0x00000000); nvme_write_reg(NVME_ASQ + 0x48, 0x00000000); nvme_write_reg(NVME_ASQ + 0x4C, 0x00000000); nvme_write_reg(NVME_ASQ + 0x50, 0x00000000); nvme_write_reg(NVME_ASQ + 0x54, 0x00000000); nvme_write_reg(NVME_ASQ + 0x58, 0x00000000); nvme_write_reg(NVME_ASQ + 0x5C, 0x00000000); nvme_write_reg(NVME_ASQ + 0x60, 0x00000000); nvme_write_reg(NVME_ASQ + 0x64, 0x00000000); nvme_write_reg(NVME_ASQ + 0x68, 0x00000000); nvme_write_reg(NVME_ASQ + 0x6C, 0x00000000); nvme_write_reg(NVME_ASQ + 0x70, 0x00000000); nvme_write_reg(NVME_ASQ + 0x74, 0x00000000); nvme_write_reg(NVME_ASQ + 0x78, 0x00000000); nvme_write_reg(NVME_ASQ + 0x7C, 0x00000000); nvme_write_reg(NVME_ASQ + 0x80, 0x00000000); nvme_write_reg(NVME_ASQ + 0x84, 0x00000000); nvme_write_reg(NVME_ASQ + 0x88, 0x00000000); nvme_write_reg(NVME_ASQ + 0x8C, 0x00000000); nvme_write_reg(NVME_ASQ + 0x90, 0x00000000); nvme_write_reg(NVME_ASQ + 0x94, 0x00000000); nvme_write_reg(NVME_ASQ + 0x98, 0x00000000); nvme_write_reg(NVME_ASQ + 0x9C, 0x00000000); nvme_write_reg(NVME_ASQ + 0xA0, 0x00000000); nvme_write_reg(NVME_ASQ + 0xA4, 0x00000000); nvme_write_reg(NVME_ASQ + 0xA8, 0x00000000); nvme_write_reg(NVME_ASQ + 0xAC, 0x00000000); nvme_write_reg(NVME_ASQ + 0xB0, 0x00000000); nvme_write_reg(NVME_ASQ + 0xB4, 0x00000000); nvme_write_reg(NVME_ASQ + 0xB8, 0x00000000); nvme_write_reg(NVME_ASQ + 0xBC, 0x00000000); nvme_write_reg(NVME_ASQ + 0xC0, 0x00000000); nvme_write_reg(NVME_ASQ + 0xC4, 0x00000000); nvme_write_reg(NVME_ASQ + 0xC8, 0x00000000); nvme_write_reg(NVME_ASQ + 0xCC, 0x00000000); nvme_write_reg(NVME_ASQ + 0xD0, 0x00000000); nvme_write_reg(NVME_ASQ + 0xD4, 0x00000000); nvme_write_reg(NVME_ASQ + 0xD8, 0x00000000); nvme_write_reg(NVME_ASQ + 0xDC, 0x00000000); nvme_write_reg(NVME_ASQ + 0xE0, 0x00000000); nvme_write_reg(NVME_ASQ + 0xE4, 0x00000000); nvme_write_reg(NVME_ASQ + 0xE8, 0x00000000); nvme_write_reg(NVME_ASQ + 0xEC, 0x00000000); nvme_write_reg(NVME_ASQ + 0xF0, 0x00000000); nvme_write_reg(NVME_ASQ + 0xF4, 0x00000000); nvme_write_reg(NVME_ASQ + 0xF8, 0x00000000); nvme_write_reg(NVME_ASQ + 0xFC, 0x00000001); // Wait for the command to complete while ((nvme_read_reg(NVME_CSTS) & 0x00000002) == 0); // Read the Identify Controller data u32 *identify_controller_data = (u32 *)(NVME_BAR1_ADDR + 0x1000); for (int i = 0; i < 16; i++) { xil_printf("Identify Controller data[%d]: 0x%08X\n", i, identify_controller_data[i]); } return 0; } ``` 该例程首先重置NVMe控制器,然后配置控制器并等待其准备好。然后,该例程发出一个Identify Controller命令,读取Identify Controller数据,并打印该数据。请注意,此示例代码仅用于参考,需要根据实际情况进行修改。

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