Error (10663): Verilog HDL Port Connection error at floatMulit32.v(16): output or inout port “sign” must be connected to a structural net expression 这个属于实例化的时候参数类型不正确,将reg类型改为wire
Error (12007): Top-level design entity “floatMulit32” is undefined 这个是你最外层的模块名要和你的工程名字一致